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Fixed CPU clocks - DRAM crashes above 200 Mhz (?)

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This commit is contained in:
claudiol 2021-01-06 08:18:44 -05:00
parent f7d0bddaea
commit 7c599fbec6
8 changed files with 42 additions and 18 deletions
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6
firmware/hal_battery_primeg1.c
View file

@ -68,7 +68,7 @@ void battery_handler()
// THIS IS THE REAL HANDLER
if(__battery < 0x300) {
if(__battery < 0x60) {
// SHOW CRITICAL BATTERY SIGNAL
if(halFlags & HAL_FASTMODE) {
// LOW VOLTAGE WHEN RUNNING FAST
@ -90,7 +90,7 @@ void battery_handler()
return;
}
if(__battery < 0x320) {
if(__battery < 0x62) {
// SHOW STATIC LOW BATTERY SIGNAL
if(halFlags & HAL_FASTMODE) {
// LOW VOLTAGE WHEN RUNNING FAST IS OK
@ -118,7 +118,7 @@ void battery_handler()
return;
}
if(__battery >= 0x320) {
if(__battery >= 0x62) {
// REMOVE BATTERY INDICATOR AND ALLOW FAST MODE
if(halGetNotification(N_LOWBATTERY))
halScreenUpdated();

2
firmware/include/target_prime1.h
View file

@ -813,7 +813,7 @@ extern unsigned char const __keyb_bitfromcode[64];
#define halScreenUpdated() ((void)0)
// DEFAULT CLOCK SPEEDS
#define HAL_SLOWCLOCK 200000000
#define HAL_SLOWCLOCK 100000000
#define HAL_USBCLOCK 400000000
#define HAL_FASTCLOCK 400000000

8
firmware/sys/target_prime1/battery.c
View file

@ -24,6 +24,8 @@ void bat_setup()
*ADCCON=0x7fc2; // Enable prescaler, maximum prescaler=0xff, start by Read
*ADCTSC = 0xd8; // YM 2 ground switch enable, YP to VDD disable, XM to GND disable, XP to VDD disable, PULL_UP disable
__battery = *ADCDAT0 & 0x3ff; // INITAL READ WILL TRIGGER FIRST CONVERSION
while(!(*ADCCON & 0x8000));
__battery = *ADCDAT0 & 0x3ff; // SECOND READ IS A GOOD VALUE
for(int k=0;k<8;++k) __bat_avg[k]=__battery;
__bat_avgidx=0;
@ -42,6 +44,12 @@ void bat_read()
while(!(*ADCCON & 0x8000));
__bat_avg[__bat_avgidx]= *ADCDAT0 & 0x3ff; // READ LAST KNOWN VALUE, AND TRIGGER A NEW ONE
if(__bat_avg[__bat_avgidx]<0x100) __bat_avg[__bat_avgidx]=0x3ff; // WHEN BATTERY IS FULLY CHARGED AD CONVERSION RETURNS 0x0nn INSTEAD OF 0x4nn, JUST MAKE IT MAXIMUM CHARGE
__bat_avgidx++;
__bat_avgidx&=7;
int count=0;
for(int k=0;k<8;++k) count += __bat_avg[k]; // AVERAGE OUT TO MAKE IT MORE STABLE

3
firmware/sys/target_prime1/boot_multiload.c
View file

@ -70,8 +70,9 @@ void printline(char *left_text, char *right_text) {
int esc_pressed() {
*GPGCON = 0; // SET ALL KEYBOARD COLUMNS AS INPUTS
*GPGUDP = 0x5555; // ENABLE PULLDOWN ON ALL INPUT LINES
*GPDCON = (*GPDCON & 0xffff0000) | 0X5555; // ALL ROWS TO OUTPUT
*GPDUDP = (*GPDUDP &0xffff0000) | 0x5555; // PULL DOWN ENABLE ON ALL OUTPUTS (TEMPORARILY SET TO INPUTS DURING SCAN)
*GPDDAT &= 0xffff0000; // ALL ROWS LOW
*GPDDAT |= (1 << 6);

2
firmware/sys/target_prime1/boot_prime1.c
View file

@ -873,7 +873,7 @@ void startup(void)
}
*RSTSTAT=0x3f;
*WKUPSTAT=0x33;
*WKUPSTAT=0x33;lcd_initspidisplay();
*/
disable_mmu();

16
firmware/sys/target_prime1/cpu.c
View file

@ -64,9 +64,9 @@ void __cpu_inton(INTERRUPT_TYPE state)
// Valid clocks for this target:
// 400000000 = 400MHz:
// MSysCLK = 800 MHz ; ARMCLK = 400 MHz, HCLK = 133 MHz, PCLK = 66 MHz, DDRCLK=2*HCLK=266 MHz
// MSysCLK = 400 MHz ; ARMCLK = 400 MHz, HCLK = 100 MHz, PCLK = 50 MHz, DDRCLK=2*HCLK=200 MHz
// 200000000 = 200MHz:
// MSysCLK = 800 MHz ; ARMCLK = 200 MHz, HCLK = 100 MHz, PCLK = 50 MHz, DDRCLK=2*HCLK=200 MHz
// MSysCLK = 400 MHz ; ARMCLK = 200 MHz, HCLK = 100 MHz, PCLK = 50 MHz, DDRCLK=2*HCLK=200 MHz
// Given a PLL configuration, set the clock and adjust all other hardware clocks to comply with specs
@ -84,7 +84,7 @@ int __cpu_setspeed(unsigned int mode)
// Check if LCD is already on, then adjust cpu speed only at end of frame
// and fix the LCD frequency
if(*VIDCON0&3) {
*VIDCON0 &= ~1; // Request LCD signals off at end of current frame
*VIDCON0 = (*VIDCON0&~3)|0x2; // Request LCD signals off at end of current frame
while(*VIDCON0&1) ; // And wait for it to happen
}
@ -92,13 +92,13 @@ int __cpu_setspeed(unsigned int mode)
switch(mode)
{
case 400:
// MSysCLK = 800 MHz ; ARMCLK = 400 MHz, HCLK = 133 MHz, PCLK = 66 MHz, DDRCLK=2*HCLK=266 MHz
// MSysCLK = 400 MHz ; ARMCLK = 400 MHz, HCLK = 100 MHz, PCLK = 50 MHz, DDRCLK=2*HCLK=200 MHz
// Max. performance MsysCLK = 800 MHz
// MDIV PDIV SDIV
*MPLLCON = (400<<14) | (3<<5) | (1);
*MPLLCON= (400<<14) | (3<<5) | (2);
// ARMDIV PREDIV PCLKDIV HCLKDIV
*CLKDIV0 = (1<<9) | (2<<4) | (1<<2) | (1) ;
*CLKDIV0 = (0<<9) | (1<<4) | (1<<2) | (1) ;
break;
case 200:
// MSysCLK = 400 MHz ; ARMCLK = 200 MHz, HCLK = 100 MHz, PCLK = 50 MHz, DDRCLK=2*HCLK=200 MHz
@ -281,6 +281,10 @@ __ARM_MODE__ void cpu_off_prepare()
lcd_off();
// SET GPB9 and GPF4 TO ZERO TO POWER DOWN THE LCD CHIP
*GPBDAT = (*GPBDAT & ~0x200); // GPB9 POWER UP THE LCD DRIVER CHIP
*GPFDAT = (*GPFDAT & ~0x10); // GPF4 POWER UP THE LCD DRIVER CHIP
asm volatile ("mov r0,r0"); // USE NOPS AS BARRIER TO FORCE COMPILER TO RESPECT THE ORDER
// PREPARE ALL GPIO BLOCKS FOR POWEROFF

18
firmware/sys/target_prime1/lcd.c
View file

@ -10,6 +10,9 @@
int __lcd_contrast __SYSTEM_GLOBAL__;
// Function supplied by CPU module, returns the hardware clock frequency in Hertz
extern int __cpu_getHCLK();
void lcd_sync()
{
@ -85,7 +88,7 @@ void lcd_setcontrast(int level)
#define SET_DATA(a) *GPHDAT=(*GPHDAT&~0x10)|((a)? 0x10:0)
#define DELAY_ONETICK tmr_delayus(1000)
#define DELAY_ONETICK tmr_delayms(1)
void lcd_sendi2c(int cmd,int data)
{
@ -157,12 +160,20 @@ void lcd_initspidisplay()
*GPBCON = (*GPBCON & (~0xc0000)) | 0x40000; // GPB9 SET TO OUTPUT (POWER TO LCD DRIVER CHIP)
*GPBUDP = (*GPBUDP & (~0xc0000)); // GPB9 DISABLE PULLUP/DOWN
*GPFCON = (*GPFCON & (~0x300)) | 0x100; // GPF4 SET TO OUTPUT (POWER TO LCD DRIVER CHIP)
*GPFUDP = (*GPFUDP & (~0x300)); // GPF4 DISABLE PULLUP/DOWN
// SET BOTH TO ZERO TO RESET THE CHIP
*GPBDAT = (*GPBDAT & ~0x200); // GPB9 POWER UP THE LCD DRIVER CHIP
*GPFDAT = (*GPFDAT & ~0x10); // GPF4 POWER UP THE LCD DRIVER CHIP
DELAY_ONETICK;
*GPBDAT = (*GPBDAT | 0x200); // GPB9 POWER UP THE LCD DRIVER CHIP
DELAY_ONETICK;
*GPFCON = (*GPFCON & (~0x300)) | 0x100; // GPF4 SET TO OUTPUT (POWER TO LCD DRIVER CHIP)
*GPFUDP = (*GPFUDP & (~0x300)); // GPF4 DISABLE PULLUP/DOWN
*GPFDAT = (*GPFDAT | 0x10); // GPF4 POWER UP THE LCD DRIVER CHIP
DELAY_ONETICK;
@ -195,6 +206,7 @@ void lcd_initspidisplay()
lcd_sendi2c(0x17,0x62);
}

5
firmware/sys/target_prime1/timer.c
View file

@ -306,11 +306,10 @@ void tmr_delayus(int microseconds)
if(microseconds <= 0)
return;
unsigned long long start = tmr_ticks();
tmr_t start = tmr_ticks();
// CALCULATE ENDING TICKS
unsigned long long end =
start + ((microseconds * tmr_getsysfreq()) / 1000000);
tmr_t end = start + ((microseconds * tmr_getsysfreq()) / 1000000);
// AND WAIT
while(end > tmr_ticks());