- Update to Softloat 3 from 2
- FREM and FMOD now generate the quotient bits in FPSR, required by Apple's SANE to do sin/cos/tan properly.
- FMOVE of a float to a Dx integer register generates the exception status bits, fixing square roots in SANE
- Rewrote how FMOVEM instructions are decoded and executed, fixing issues including skipping too few or too many
opcode bytes and causing serious weird behavior.
- FPU instructions all now have more realistic cycle timings for a 68881.
- All FPU instructions now generate exception bits in FPSR.
3rdparty/softfloat3: Updates [R. Belmont]
- Softfloat3 was always being built for a big-endian host, causing incorrect math on LE x64 and AArch64 machines.
- Fixed up Softfloat3 to build properly as part of MAME and up-ported the Bochs extensions. In latest Bochs, they
were only partially up-ported and Softfloat3 had been hacked up to be more like 2; here they're fixed to work
with stock Softfloat3.
