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https://github.com/mamedev/mame.git
synced 2024-11-16 07:48:32 +01:00
cmi2x: Modernization and cleanup
- Use interrupt vector read callbacks to handle context switching and special IRQ and RESET vectoring - Use addressable latch device for CPU function register
This commit is contained in:
AJR
parent
0480765f07
commit
ec77693858
1 changed files with 62 additions and 96 deletions
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@ -91,6 +91,7 @@
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#include "machine/6821pia.h"
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#include "machine/6850acia.h"
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#include "machine/6840ptm.h"
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#include "machine/74259.h"
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#include "machine/7474.h"
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#include "machine/bankdev.h"
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#include "machine/clock.h"
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@ -257,8 +258,8 @@ public:
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void q133_1_portb_w(u8 data);
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void cmi_iix_vblank(int state);
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IRQ_CALLBACK_MEMBER(cpu1_interrupt_callback);
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IRQ_CALLBACK_MEMBER(cpu2_interrupt_callback);
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u8 vfetch1_r(offs_t offset);
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u8 vfetch2_r(offs_t offset);
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// Video-related
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u8 video_r(offs_t offset);
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@ -290,19 +291,16 @@ public:
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// Memory mapping
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template<int CpuNum> u8 rom_r(offs_t offset);
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void map_ram_w(offs_t offset, u8 data);
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template<int CpuNum> u8 vector_r(offs_t offset);
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template<int CpuNum> u8 map_r();
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template<int CpuNum> void map_w(u8 data);
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u8 atomic_r();
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void cpufunc_w(u8 data);
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template<int CpuNum> void ipi_w(int state);
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template<int CpuNum> void nmi_reset_w(int state);
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template<int CpuNum> void ms_w(int state);
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u8 parity_r(offs_t offset);
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void mapsel_w(offs_t offset, u8 data);
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template<int CpuNum> u8 irq_ram_r(offs_t offset);
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template<int CpuNum> void irq_ram_w(offs_t offset, u8 data);
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template<int CpuNum> u8 scratch_ram_r(offs_t offset);
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template<int CpuNum> void scratch_ram_w(offs_t offset, u8 data);
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template<int CpuNum> u8 scratch_ram_fa_r(offs_t offset);
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template<int CpuNum> void scratch_ram_fa_w(offs_t offset, u8 data);
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// MIDI/SMPTE
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void midi_dma_w(offs_t offset, u16 data, u16 mem_mask = ~0);
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@ -432,8 +430,6 @@ private:
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int m_cpu_active_space[2]{};
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int m_cpu_map_switch[2]{};
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u8 m_curr_mapinfo[2]{};
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u8 m_irq_address[2][2]{};
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int m_m6809_bs_hack_cnt[2]{};
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/* Q219 lightpen/graphics card */
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std::unique_ptr<u8[]> m_video_ram;
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@ -915,11 +911,6 @@ void cmi_state::map_ram_w(offs_t offset, u8 data)
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}
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}
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template<int CpuNum> u8 cmi_state::vector_r(offs_t offset)
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{
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return m_q133_rom[(CpuNum ? 0xbfe : 0xffe) + offset];
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}
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template<int CpuNum> u8 cmi_state::map_r()
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{
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return (m_cpu_active_space[1] << 2) | (m_cpu_active_space[0] << 1) | CpuNum;
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@ -930,25 +921,6 @@ template<int CpuNum> void cmi_state::map_w(u8 data)
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m_map_switch_timer->adjust(attotime::from_ticks(data & 0xf, M6809_CLOCK), CpuNum);
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}
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template<int CpuNum> u8 cmi_state::irq_ram_r(offs_t offset)
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{
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if (machine().side_effects_disabled())
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return m_scratch_ram[CpuNum][0xf8 + offset];
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if (m_m6809_bs_hack_cnt[CpuNum] > 0)
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{
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m_m6809_bs_hack_cnt[CpuNum]--;
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LOG("CPU%d IRQ vector byte %d (offset %d): %02x\n", CpuNum + 1, 1 - m_m6809_bs_hack_cnt[CpuNum], offset, m_irq_address[CpuNum][offset]);
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return m_irq_address[CpuNum][offset];
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}
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return m_scratch_ram[CpuNum][0xf8 + offset];
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}
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template<int CpuNum> void cmi_state::irq_ram_w(offs_t offset, u8 data)
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{
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m_scratch_ram[CpuNum][0xf8 + offset] = data;
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}
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TIMER_CALLBACK_MEMBER(cmi_state::switch_map)
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{
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m_cpu_active_space[param] = m_cpu_map_switch[param];
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@ -972,26 +944,19 @@ u8 cmi_state::atomic_r()
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return 0;
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}
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void cmi_state::cpufunc_w(u8 data)
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template<int CpuNum> void cmi_state::ipi_w(int state)
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{
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int cpunum = data & 1;
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int idx = data & 6;
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int bit = (data & 8) >> 3;
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set_interrupt(CpuNum, IRQ_IPI2_LEVEL, state ? ASSERT_LINE : CLEAR_LINE);
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}
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switch (idx)
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{
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case 0: set_interrupt(cpunum, IRQ_IPI2_LEVEL, bit ? ASSERT_LINE : CLEAR_LINE);
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break;
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case 2: // TODO: Hardware trace
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break;
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case 4: m_cpu_map_switch[cpunum] = bit;
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break;
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case 6: if (cpunum == CPU_1)
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m_maincpu1->set_input_line(M6809_FIRQ_LINE, bit ? ASSERT_LINE : CLEAR_LINE);
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else
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m_maincpu2->set_input_line(M6809_FIRQ_LINE, bit ? ASSERT_LINE : CLEAR_LINE);
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break;
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}
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template<int CpuNum> void cmi_state::nmi_reset_w(int state)
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{
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// TODO: Hardware trace
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}
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template<int CpuNum> void cmi_state::ms_w(int state)
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{
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m_cpu_map_switch[CpuNum] = state;
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}
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u8 cmi_state::parity_r(offs_t offset)
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@ -1140,7 +1105,7 @@ template <int CpuNum> void cmi_state::cpu_periphs_map(address_map &map)
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map(0x0800, 0x0bff).rom().region("q133", 0x2800 - CpuNum * 0x1000);
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map(0x0c40, 0x0c4f).rw(FUNC(cmi_state::parity_r), FUNC(cmi_state::mapsel_w));
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map(0x0c5a, 0x0c5b).noprw(); // Q077 HDD controller - not installed
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map(0x0c5e, 0x0c5e).rw(FUNC(cmi_state::atomic_r), FUNC(cmi_state::cpufunc_w));
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map(0x0c5e, 0x0c5e).r(FUNC(cmi_state::atomic_r)).w("cpulatch", FUNC(ls259_device::write_nibble_d3));
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map(0x0c5f, 0x0c5f).rw(FUNC(cmi_state::map_r<CpuNum>), FUNC(cmi_state::map_w<CpuNum>));
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map(0x0c80, 0x0c83).rw(m_q133_acia[0], FUNC(mos6551_device::read), FUNC(mos6551_device::write));
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map(0x0c84, 0x0c87).rw(m_q133_acia[1], FUNC(mos6551_device::read), FUNC(mos6551_device::write));
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@ -1160,10 +1125,7 @@ template <int CpuNum> void cmi_state::cpu_periphs_map(address_map &map)
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map(0x0cfc, 0x0cfc).w(FUNC(cmi_state::i8214_cpu1_w));
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map(0x0cfd, 0x0cfd).w(FUNC(cmi_state::i8214_cpu2_w));
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map(0x0d00, 0x0eff).rw(FUNC(cmi_state::shared_ram_r), FUNC(cmi_state::shared_ram_w));
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map(0x0f00, 0x0ff7).rw(FUNC(cmi_state::scratch_ram_r<CpuNum>), FUNC(cmi_state::scratch_ram_w<CpuNum>));
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map(0x0ff8, 0x0ff9).rw(FUNC(cmi_state::irq_ram_r<CpuNum>), FUNC(cmi_state::irq_ram_w<CpuNum>));
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map(0x0ffa, 0x0ffd).rw(FUNC(cmi_state::scratch_ram_fa_r<CpuNum>), FUNC(cmi_state::scratch_ram_fa_w<CpuNum>));
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map(0x0ffe, 0x0fff).r(FUNC(cmi_state::vector_r<CpuNum>));
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map(0x0f00, 0x0fff).rw(FUNC(cmi_state::scratch_ram_r<CpuNum>), FUNC(cmi_state::scratch_ram_w<CpuNum>));
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}
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/* Input ports */
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@ -1188,16 +1150,6 @@ template <int CpuNum> void cmi_state::scratch_ram_w(offs_t offset, u8 data)
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m_scratch_ram[CpuNum][offset] = data;
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}
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template <int CpuNum> u8 cmi_state::scratch_ram_fa_r(offs_t offset)
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{
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return m_scratch_ram[CpuNum][0xfa + offset];
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}
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template <int CpuNum> void cmi_state::scratch_ram_fa_w(offs_t offset, u8 data)
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{
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m_scratch_ram[CpuNum][0xfa + offset] = data;
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}
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bool cmi_state::map_is_active(int cpunum, int map, u8 *map_info)
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{
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if (m_cpu_active_space[cpunum] == MAPPING_A)
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@ -1720,48 +1672,57 @@ void cmi_state::ptm_q219_irq(int state)
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set_interrupt(CPU_2, IRQ_RINT_LEVEL, state);
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}
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IRQ_CALLBACK_MEMBER( cmi_state::cpu1_interrupt_callback )
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u8 cmi_state::vfetch1_r(offs_t offset)
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{
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/* Switch to mapping A */
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// Switch to mapping A
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m_cpu_active_space[CPU_1] = MAPPING_A;
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update_address_space(CPU_1, m_map_sel[MAPSEL_P1_A]);
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if (irqline == INPUT_LINE_IRQ0)
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if ((offset & 0x000e) == 0x0008)
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{
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// IRQ vector
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int vector = (m_hp_int ? 0xffe0 : 0xffd0);
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int level = (m_hp_int ? m_i8214[2]->a_r() : m_i8214[0]->a_r()) ^ 7;
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m_irq_address[CPU_1][0] = m_cpu1space->read_byte(vector + level*2);
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m_irq_address[CPU_1][1] = m_cpu1space->read_byte(vector + level*2 + 1);
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m_m6809_bs_hack_cnt[CPU_1] = 2;
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LOG("%s: CPU1 interrupt, will be pushing address %02x%02x\n", machine().describe_context(), m_irq_address[CPU_1][0], m_irq_address[CPU_1][1]);
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u8 irq_address = m_cpu1space->read_byte(vector + level * 2 + BIT(offset, 0));
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LOG("%s: CPU1 IRQ vector %s byte: %02x\n", machine().describe_context(), BIT(offset, 0) ? "low" : "high", irq_address);
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return irq_address;
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}
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else if ((offset & 0x000e) == 0x000e)
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{
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// RESET vector
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return m_q133_rom[offset & 0xfff];
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}
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else
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{
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LOG("%s: Some other CPU1 interrupt, line %d\n", irqline);
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LOG("%s: Some other CPU1 interrupt, fetching vector from $%04x\n", machine().describe_context(), offset);
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return m_scratch_ram[CPU_1][offset & 0xff];
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}
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return 0;
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}
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IRQ_CALLBACK_MEMBER( cmi_state::cpu2_interrupt_callback )
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u8 cmi_state::vfetch2_r(offs_t offset)
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{
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/* Switch to mapping A */
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// Switch to mapping A
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m_cpu_active_space[CPU_2] = MAPPING_A;
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update_address_space(CPU_2, m_map_sel[MAPSEL_P2_A]);
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if (irqline == INPUT_LINE_IRQ0)
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if ((offset & 0x000e) == 0x0008)
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{
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// IRQ vector
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int level = m_i8214[1]->a_r() ^ 7;
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m_irq_address[CPU_2][0] = m_cpu2space->read_byte(0xffe0 + level*2);
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m_irq_address[CPU_2][1] = m_cpu2space->read_byte(0xffe0 + level*2 + 1);
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m_m6809_bs_hack_cnt[CPU_2] = 2;
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//osd_printf_debug("cpu1 interrupt, will be pushing address %02x%02x\n", m_irq_address[CPU_2][0], m_irq_address[CPU_2][1]);
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u8 irq_address = m_cpu2space->read_byte(0xffe0 + level*2 + BIT(offset, 0));
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LOG("%s: CPU2 IRQ vector %s byte: %02x (%s)\n", machine().describe_context(), BIT(offset, 0) ? "low" : "high", irq_address);
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return irq_address;
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}
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else if ((offset & 0x000e) == 0x000e)
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{
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// RESET vector
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return m_q133_rom[offset & 0xbff];
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}
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else
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{
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LOG("%s: Some other CPU2 interrupt, fetching vector from $%04x\n", machine().describe_context(), offset);
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return m_scratch_ram[CPU_2][offset & 0xff];
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}
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return 0;
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}
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void cmi_state::set_interrupt(int cpunum, int level, int state)
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@ -1931,9 +1892,6 @@ void cmi_state::machine_reset()
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/* Select A (system) spaces */
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m_cpu_active_space[cpunum] = MAPPING_A;
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m_irq_address[cpunum][0] = space->read_byte(0xfff8);
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m_irq_address[cpunum][1] = space->read_byte(0xfff9);
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}
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// TODO - we need to detect empty disk drive!!
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@ -1954,8 +1912,6 @@ void cmi_state::machine_reset()
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m_cmi02_ptm->set_g1(0);
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m_cmi02_ptm->set_g2(0);
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m_cmi02_ptm->set_g3(0);
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m_m6809_bs_hack_cnt[0] = 0;
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m_m6809_bs_hack_cnt[1] = 0;
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//m_midi_ptm[0]->set_g1(1); // /G1 has unknown source, "TIMER 1A /GATE" per schematic
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m_midi_ptm[0]->set_g2(0); // /G2 and /G3 wired to ground per schematic
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@ -2034,11 +1990,11 @@ void cmi_state::cmi2x(machine_config &config)
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{
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MC6809E(config, m_maincpu1, Q209_CPU_CLOCK);
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m_maincpu1->set_addrmap(AS_PROGRAM, &cmi_state::maincpu1_map);
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m_maincpu1->set_irq_acknowledge_callback(FUNC(cmi_state::cpu1_interrupt_callback));
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m_maincpu1->interrupt_vector_read().set(FUNC(cmi_state::vfetch1_r));
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MC6809E(config, m_maincpu2, Q209_CPU_CLOCK);
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m_maincpu2->set_addrmap(AS_PROGRAM, &cmi_state::maincpu2_map);
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m_maincpu2->set_irq_acknowledge_callback(FUNC(cmi_state::cpu2_interrupt_callback));
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m_maincpu2->interrupt_vector_read().set(FUNC(cmi_state::vfetch2_r));
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ADDRESS_MAP_BANK(config, m_cpu_periphs[0]).set_options(ENDIANNESS_BIG, 8, 16, 0x1000);
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m_cpu_periphs[0]->set_addrmap(AS_PROGRAM, &cmi_state::cpu_periphs_map<0>);
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@ -2046,6 +2002,16 @@ void cmi_state::cmi2x(machine_config &config)
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ADDRESS_MAP_BANK(config, m_cpu_periphs[1]).set_options(ENDIANNESS_BIG, 8, 16, 0x1000);
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m_cpu_periphs[1]->set_addrmap(AS_PROGRAM, &cmi_state::cpu_periphs_map<1>);
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ls259_device &cpulatch(LS259(config, "cpulatch")); // 6D (Q209)
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cpulatch.q_out_cb<0>().set(FUNC(cmi_state::ipi_w<0>));
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cpulatch.q_out_cb<1>().set(FUNC(cmi_state::ipi_w<1>));
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cpulatch.q_out_cb<2>().set(FUNC(cmi_state::nmi_reset_w<0>));
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cpulatch.q_out_cb<3>().set(FUNC(cmi_state::nmi_reset_w<1>));
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cpulatch.q_out_cb<4>().set(FUNC(cmi_state::ms_w<0>));
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cpulatch.q_out_cb<5>().set(FUNC(cmi_state::ms_w<1>));
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cpulatch.q_out_cb<6>().set_inputline(m_maincpu1, M6809_FIRQ_LINE);
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cpulatch.q_out_cb<7>().set_inputline(m_maincpu2, M6809_FIRQ_LINE);
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M68000(config, m_midicpu, 20_MHz_XTAL / 2);
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m_midicpu->set_addrmap(AS_PROGRAM, &cmi_state::midicpu_map);
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