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synced 2024-11-16 07:48:32 +01:00
Some work towards Aqua Stage, looks like both SH-2/SH-1 shared RAMs addresses can be modified somehow. It currently asks for attendant if out of service mode (which is probably the purpose of the extra input field I suppose). (nw)
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angelosa
parent
92775ea014
commit
e3babf8351
1 changed files with 152 additions and 1 deletions
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@ -2856,6 +2856,12 @@ static ADDRESS_MAP_START( system_h1_map, AS_PROGRAM, 32, coolridr_state )
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AM_RANGE(0x60000000, 0x600003ff) AM_WRITENOP
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(aquastge_h1_map, AS_PROGRAM, 32, coolridr_state)
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AM_RANGE(0x03c00000, 0x03c0ffff) AM_MIRROR(0x00200000) AM_RAM_WRITE(sysh1_dma_w) AM_SHARE("fb_vram") /* mostly mapped at 0x03e00000 */
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AM_RANGE(0x03e10000, 0x03e1ffff) AM_RAM AM_SHARE("share3") /*Communication area RAM*/
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AM_RANGE(0x03f00000, 0x03f0ffff) AM_RAM AM_SHARE("share3") /*Communication area RAM*/
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AM_IMPORT_FROM(system_h1_map)
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ADDRESS_MAP_END
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READ16_MEMBER( coolridr_state::h1_soundram_r)
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{
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@ -3034,6 +3040,15 @@ static ADDRESS_MAP_START( coolridr_submap, AS_PROGRAM, 32, coolridr_state )
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AM_RANGE(0x60000000, 0x600003ff) AM_WRITENOP
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( aquastge_submap, AS_PROGRAM, 32, coolridr_state )
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AM_RANGE(0x05210000, 0x0521ffff) AM_RAM AM_SHARE("share3") /*Communication area RAM*/
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AM_RANGE(0x05200000, 0x0537ffff) AM_RAM
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AM_RANGE(0x06000200, 0x06000207) AM_WRITENOP // program bug?
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AM_RANGE(0x06100018, 0x0610001b) AM_READ_PORT("IN7")
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AM_IMPORT_FROM(coolridr_submap)
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ADDRESS_MAP_END
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/* TODO: what is this for, volume mixing? MIDI? */
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WRITE8_MEMBER(coolridr_state::sound_to_sh1_w)
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{
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@ -3057,6 +3072,134 @@ static GFXDECODE_START( coolridr )
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// GFXDECODE_ENTRY( NULL, 0, tiles16x16_layout, 0, 0x100 )
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GFXDECODE_END
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#define DUMMY_INPUT_PORT(_x_) \
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PORT_START(_x_) \
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PORT_DIPNAME( 0x00000001, 0x00000001, _x_ ) \
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PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00010000, 0x00010000, _x_ ) \
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PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00020000, 0x00020000, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) ) \
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PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) ) \
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
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PORT_BIT( 0xff00ff00, IP_ACTIVE_LOW, IPT_UNUSED ) \
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static INPUT_PORTS_START( aquastge )
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DUMMY_INPUT_PORT("IN0")
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PORT_START("IN1")
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PORT_DIPNAME( 0x00000001, 0x00000001, "IN1" )
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PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
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PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
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PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("P1 Coin")
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PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("P2 Coin")
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PORT_SERVICE_NO_TOGGLE( 0x00040000, IP_ACTIVE_LOW )
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PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("P1 Service Switch")
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PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("P1 Start")
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PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("P2 Start")
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PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("P2 Service Switch")
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PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0xff00ff00, IP_ACTIVE_LOW, IPT_UNUSED )
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DUMMY_INPUT_PORT("IN2")
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DUMMY_INPUT_PORT("IN3")
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DUMMY_INPUT_PORT("IN5")
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DUMMY_INPUT_PORT("IN6")
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DUMMY_INPUT_PORT("IN7")
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PORT_START("AN0")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("AN1")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("AN2")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("AN3")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("AN4")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("AN5")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("AN6")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("AN7")
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PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
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// driver debug
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PORT_START("CONFIG")
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PORT_CONFNAME( 0x01, 0x01, "Use Threading Code" )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x01, DEF_STR( On ) )
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INPUT_PORTS_END
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static INPUT_PORTS_START( coolridr )
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PORT_START("IN0")
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PORT_DIPNAME( 0x00000001, 0x00000001, "IN0-0" )
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@ -3623,6 +3766,14 @@ static MACHINE_CONFIG_START( coolridr, coolridr_state )
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MCFG_SOUND_ROUTE(0, "rspeaker", 1.0)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( aquastge, coolridr )
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MCFG_CPU_MODIFY("maincpu")
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MCFG_CPU_PROGRAM_MAP(aquastge_h1_map)
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MCFG_CPU_MODIFY("sub")
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MCFG_CPU_PROGRAM_MAP(aquastge_submap)
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MACHINE_CONFIG_END
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ROM_START( coolridr )
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ROM_REGION( 0x200000, "maincpu", 0 ) /* SH2 code */
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ROM_LOAD32_WORD_SWAP( "ep17659.30", 0x0000000, 0x080000, CRC(473027b0) SHA1(acaa212869dd79550235171b9f054e82750f74c3) )
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@ -3797,5 +3948,5 @@ DRIVER_INIT_MEMBER(coolridr_state, aquastge)
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}
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GAME( 1995, coolridr, 0, coolridr, coolridr, coolridr_state, coolridr, ROT0, "Sega", "Cool Riders",GAME_IMPERFECT_SOUND) // region is set in test mode, this set is for Japan, USA and Export (all regions)
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GAME( 1995, aquastge, 0, coolridr, coolridr, coolridr_state, aquastge, ROT0, "Sega", "Aqua Stage",GAME_NOT_WORKING)
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GAME( 1995, aquastge, 0, aquastge, aquastge, coolridr_state, aquastge, ROT0, "Sega", "Aqua Stage",GAME_NOT_WORKING)
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