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vme/enp10: add new device [CJ, System Source Computer Museum]
This commit is contained in:
Patrick Mackinlay
parent
f83830751a
commit
b877d9c15e
3 changed files with 219 additions and 0 deletions
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@ -2641,6 +2641,8 @@ end
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if (BUSES["VME"]~=null) then
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files {
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MAME_DIR .. "src/devices/bus/vme/enp10.cpp",
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MAME_DIR .. "src/devices/bus/vme/enp10.h",
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MAME_DIR .. "src/devices/bus/vme/mvme187.cpp",
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MAME_DIR .. "src/devices/bus/vme/mvme187.h",
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MAME_DIR .. "src/devices/bus/vme/tp881v.cpp",
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166
src/devices/bus/vme/enp10.cpp
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166
src/devices/bus/vme/enp10.cpp
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@ -0,0 +1,166 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* Communication Machinery Corporation Ethernet Node Processor (ENP-10)
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*
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* Sources:
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* - Ethernet Node Processor ENP-30 Reference Guide (6213000-05B), Communication Machinery Corporation, November 15, 1988
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*
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* TODO:
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* - vme interface
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* - address/interrupt configuration
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* - verify registers
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* - uart?
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*/
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/*
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* WIP
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* ---
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* - 0xef'8010-0xef'802f appears to be a uart, but doesn't match scn2681 per ENP-30 documentation?
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* - following text is output to 0xef'008025 at startup:
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* CMC ENP/10 CMOS - 112708 Bytes Free
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* Ethernet Address: 02CF1F123456
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* Allocating 30 receive buffers
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* Allocating 30 transmit buffers
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*/
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#include "emu.h"
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#include "enp10.h"
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#define VERBOSE 0
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(CMC_ENP10, cmc_enp10_device, "cmc_enp10", "CMC ENP-10")
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cmc_enp10_device::cmc_enp10_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: device_t(mconfig, CMC_ENP10, tag, owner, clock)
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, device_vme_card_interface(mconfig, *this)
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, m_cpu(*this, "cpu")
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, m_net(*this, "net")
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, m_led(*this, "led%u", 0U)
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, m_boot(*this, "boot")
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{
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}
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ROM_START(enp10)
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ROM_REGION16_BE(0x4000, "eprom", 0)
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ROM_SYSTEM_BIOS(0, "enp10", "CMC ENP/10 CMOS")
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ROMX_LOAD("link_10_2.0_nh_rev.4.1h.u4", 0x0000, 0x2000, CRC(7532f2b1) SHA1(bdef6c525f451fbc67f3d4625c9db18975e7e1e4), ROM_SKIP(1) | ROM_BIOS(0)) // AM2764A
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ROMX_LOAD("link_10_2.0_nh_rev.k4.1l.u3", 0x0001, 0x2000, CRC(f2decb78) SHA1(795623274bfff6273790c30445e4dca4064859ed), ROM_SKIP(1) | ROM_BIOS(0)) // AM2764A
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// hand-crafted prom containing address 02:cf:1f:12:34:56
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ROM_REGION16_BE(0x20, "mac", 0)
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ROM_LOAD("mac.bin", 0x00, 0x20, CRC(99ac9577) SHA1(b4d6bba88dd376cc492738d57742628f42e9265e))
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ROM_END
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static INPUT_PORTS_START(enp10)
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INPUT_PORTS_END
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const tiny_rom_entry *cmc_enp10_device::device_rom_region() const
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{
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return ROM_NAME(enp10);
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}
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ioport_constructor cmc_enp10_device::device_input_ports() const
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{
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return INPUT_PORTS_NAME(enp10);
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}
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void cmc_enp10_device::device_start()
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{
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m_led.resolve();
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save_item(NAME(m_ier));
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save_item(NAME(m_tir));
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save_item(NAME(m_rir));
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save_item(NAME(m_uir));
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save_item(NAME(m_exr));
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save_item(NAME(m_csr));
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save_item(NAME(m_rer));
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save_item(NAME(m_hir));
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}
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void cmc_enp10_device::device_reset()
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{
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m_boot.select(0);
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m_ier = 0;
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m_tir = 0;
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m_rir = 0;
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m_uir = 0;
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m_exr = 0;
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m_csr = 0;
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m_rer = 0;
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m_hir = 0;
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}
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void cmc_enp10_device::device_add_mconfig(machine_config &config)
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{
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M68000(config, m_cpu, 10_MHz_XTAL / 2);
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m_cpu->set_addrmap(AS_PROGRAM, &cmc_enp10_device::cpu_mem);
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AM7990(config, m_net, 20_MHz_XTAL / 2);
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m_net->intr_out().set_inputline(m_cpu, INPUT_LINE_IRQ6).invert();
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m_net->dma_in().set([this](offs_t offset) { return m_cpu->space(0).read_word(offset); });
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m_net->dma_out().set([this](offs_t offset, u16 data, u16 mem_mask) { m_cpu->space(0).write_word(offset, data, mem_mask); });
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}
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void cmc_enp10_device::cpu_mem(address_map &map)
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{
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map(0xf8'0000, 0xf8'3fff).rom().region("eprom", 0).mirror(0x02'0000);
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map(0x00'0000, 0xf1'ffff).view(m_boot);
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// map 1k of eprom at 0x00'0000
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m_boot[0](0x00'0000, 0x00'0fff).rom().region("eprom", 0);
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m_boot[0](0xf0'0000, 0xf1'ffff).ram().share("ram");
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// map 1k of ram at 0x00'0000, unmap at 0xf0'0000
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m_boot[1](0x00'0000, 0x01'ffff).ram().share("ram");
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m_boot[1](0x00'1000, 0x01'ffff).unmaprw();
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m_boot[1](0xf0'0000, 0xf1'ffff).ram().share("ram");
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m_boot[1](0xf0'0000, 0xf0'0fff).unmaprw();
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// uart: 16 byte registers 10-2f?
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map(0xef'8010, 0xef'802f).noprw();
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// fe'0080 vector? w:host vectored interrupt, r:slave address msb
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map(0xfe'00a0, 0xfe'00a1).umask16(0x00ff).lrw8(
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[this]() { return m_csr; }, "csr_r",
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[this](u8 data)
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{
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LOG("csr_w 0x%02x\n", data);
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m_led[0] = BIT(data, 6); // fail?
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m_led[1] = BIT(data, 5); // run?
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m_csr = data;
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}, "csr_w");
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map(0xfe'00c0, 0xfe'00c1).umask16(0x00ff).lrw8(NAME([this]() { return m_ier; }), NAME([this](u8 data) { m_ier = data; interrupt(); }));
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map(0xfe'00c2, 0xfe'00c3).umask16(0x00ff).lrw8(NAME([this]() { return m_tir; }), NAME([this](u8 data) { m_tir = data; interrupt(); }));
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map(0xfe'00c4, 0xfe'00c5).umask16(0x00ff).lrw8(NAME([this]() { return m_rir; }), NAME([this](u8 data) { m_rir = data; interrupt(); }));
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map(0xfe'00c6, 0xfe'00c7).umask16(0x00ff).lrw8(NAME([this]() { return m_uir; }), NAME([this](u8 data) { m_uir = data; interrupt(); }));
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map(0xfe'00ce, 0xfe'00cf).umask16(0x00ff).lrw8(NAME([this]() { return m_rer; }), NAME([this](u8 data) { m_rer = data; m_boot.select(BIT(data, 7)); }));
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map(0xfe'00e0, 0xfe'00e1).umask16(0x00ff).lrw8(NAME([this]() { return m_exr; }), NAME([this](u8 data) { m_exr = data; })); // TODO: bit 1 parity error?
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map(0xfe'00ee, 0xfe'00ef).umask16(0x00ff).lr8(NAME([]() { return 0; })); // TODO: bit 1 enables additional ram test?
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map(0xfe'0200, 0xfe'0203).rw(m_net, FUNC(am7990_device::regs_r), FUNC(am7990_device::regs_w));
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map(0xfe'0400, 0xfe'041f).rom().region("mac", 0);
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// TODO: verify the next two registers
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map(0xfe'0e00, 0xfe'0e01).umask16(0x00ff).lrw8(NAME([this]() { return m_hir; }), NAME([this](u8 data) { m_hir = data; interrupt(); }));
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map(0xfe'0f00, 0xfe'0f01).umask16(0x00ff).lrw8(NAME([this]() { reset(); return 0; }), NAME([this](u8 data) { reset(); }));
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}
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void cmc_enp10_device::interrupt()
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{
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bool const enable = BIT(m_ier, 7);
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m_cpu->set_input_line(INPUT_LINE_IRQ2, enable && BIT(m_uir, 7));
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m_cpu->set_input_line(INPUT_LINE_IRQ3, enable && BIT(m_hir, 7));
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m_cpu->set_input_line(INPUT_LINE_IRQ4, enable && BIT(m_tir, 7));
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m_cpu->set_input_line(INPUT_LINE_IRQ5, enable && BIT(m_rir, 7));
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}
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51
src/devices/bus/vme/enp10.h
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51
src/devices/bus/vme/enp10.h
Normal file
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@ -0,0 +1,51 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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#ifndef MAME_BUS_VME_ENP10_H
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#define MAME_BUS_VME_ENP10_H
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#pragma once
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#include "cpu/m68000/m68000.h"
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#include "machine/am79c90.h"
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#include "bus/vme/vme.h"
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class cmc_enp10_device
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: public device_t
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, public device_vme_card_interface
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{
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public:
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cmc_enp10_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
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protected:
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virtual const tiny_rom_entry *device_rom_region() const override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual ioport_constructor device_input_ports() const override;
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virtual void device_start() override;
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virtual void device_reset() override;
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private:
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void cpu_mem(address_map &map);
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void interrupt();
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required_device<m68000_device> m_cpu;
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required_device<am7990_device> m_net;
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output_finder<2> m_led;
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u8 m_ier; // interrupt enable register
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u8 m_tir; // transmit interrupt register
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u8 m_rir; // receive interrupt register
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u8 m_uir; // utility interrupt register
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u8 m_exr; // exception register
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u8 m_csr; // control/status register
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u8 m_rer; // ram/rom enable register
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u8 m_hir; // host interrupt register
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memory_view m_boot;
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};
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DECLARE_DEVICE_TYPE(CMC_ENP10, cmc_enp10_device)
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#endif // MAME_BUS_VME_ENP10_H
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