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machine/mediagx_host: document GP / DC maps
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parent
f25e2dbc53
commit
a0117b8263
2 changed files with 61 additions and 3 deletions
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@ -148,7 +148,7 @@ void mediagx_host_device::device_add_mconfig(machine_config &config)
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// HACK: needs an interruptible x86 core to even try.
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VGA(config, m_vga, 0);
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m_vga->set_screen("screen");
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m_vga->set_vram_size(16*1024*1024);
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m_vga->set_vram_size(4*1024*1024);
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}
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void mediagx_host_device::config_map(address_map &map)
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@ -279,14 +279,70 @@ void mediagx_host_device::gxbase_map(address_map &map)
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remap_cb();
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})
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);
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// 0x008100 GFX pipeline
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// 0x008300 Display controller
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map(0x008100, 0x0082ff).m(*this, FUNC(mediagx_host_device::gfx_pipeline_map));
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map(0x008300, 0x0083ff).m(*this, FUNC(mediagx_host_device::display_ctrl_map));
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// 0x008400 Memory controller
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// 0x008500 Power Management
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// 0x400000 SMM System Code
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// 0x800000 GFX memory
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}
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/****************************
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*
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* Graphics Pipeline
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*
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***************************/
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// GX_BASE+$8100
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void mediagx_host_device::gfx_pipeline_map(address_map &map)
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{
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// map(0x0000, 0x012f) <GP BitBLT section>
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// map(0x0140, 0x0143) GP_VGA_WRITE
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// map(0x0144, 0x0147) GP_VGA_READ
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// map(0x0200, 0x020f) <more GP BitBLT>
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// map(0x0210, 0x0213) GGP_VGA_BASE (sic?)
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// map(0x0214, 0x0217) GP_VGA_LATCH
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}
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/****************************
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*
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* Display Controller
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*
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***************************/
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// GX_BASE+$8300
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void mediagx_host_device::display_ctrl_map(address_map &map)
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{
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// map(0x0000, 0x0003) DC_UNLOCK
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// map(0x0004, 0x0007) DC_GENERAL_CFG
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// map(0x0008, 0x000b) DC_TIMING_CFG
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// map(0x000c, 0x000f) DC_OUTPUT_CFG
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// map(0x0010, 0x0013) DC_FB_ST_OFFSET
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// map(0x0014, 0x0017) DC_CB_ST_OFFSET
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// map(0x0018, 0x001b) DC_CURS_ST_OFFSET
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// map(0x0020, 0x0023) DC_VID_ST_OFFSET
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// map(0x0024, 0x0027) DC_LINE_DELTA
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// map(0x0028, 0x002b) DC_BUF_SIZE
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// map(0x0030, 0x0033) DC_H_TIMING_1
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// map(0x0033, 0x0037) DC_H_TIMING_2
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// map(0x0038, 0x003b) DC_H_TIMING_3
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// map(0x003c, 0x003f) DC_FP_H_TIMING
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// map(0x0040, 0x0043) DC_V_TIMING_1
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// map(0x0044, 0x0047) DC_V_TIMING_2
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// map(0x0048, 0x004b) DC_V_TIMING_3
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// map(0x004c, 0x004f) DC_FP_V_TIMING
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// map(0x0050, 0x0053) DC_CURSOR_X
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// map(0x0054, 0x0057) DC_V_LINE_CNT
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// map(0x0058, 0x005b) DC_CURSOR_Y
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// map(0x005c, 0x005f) DC_SS_LINE_CMP
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// map(0x0060, 0x0063) DC_CURSOR_COLOR
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// map(0x0068, 0x006b) DC_BORDER_COLOR
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// map(0x0070, 0x0073) DC_PAL_ADDRESS
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// map(0x0074, 0x0077) DC_PAL_DATA
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// map(0x0078, 0x007b) DC_DFIFO_DIAG
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// map(0x007c, 0x007f) DC_CFIFO_DIAG
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}
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void mediagx_host_device::legacy_memory_map(address_map &map)
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{
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map(0x00000, 0x1ffff).rw(FUNC(mediagx_host_device::vram_r), FUNC(mediagx_host_device::vram_w));
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@ -63,6 +63,8 @@ private:
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u8 m_pci_arbitration[2]{};
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void gxbase_map(address_map &map);
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void gfx_pipeline_map(address_map &map);
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void display_ctrl_map(address_map &map);
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u32 m_bc_xmap[3]{};
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