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hmcs40: add hmcs46/hmcs47
This commit is contained in:
hap
parent
2b906b6f90
commit
9ca21b386b
4 changed files with 191 additions and 30 deletions
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@ -53,13 +53,20 @@ DEFINE_DEVICE_TYPE(HD44820, hd44820_device, "hd44820", "Hitachi HD44820") // CMO
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DEFINE_DEVICE_TYPE(HD44828, hd44828_device, "hd44828", "Hitachi HD44828") // CMOS, low-power
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// HMCS46C/CL, 42 pins, 32 I/O lines, 4096x10 ROM, 256x4 RAM (no PMOS version exists)
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//DEFINE_DEVICE_TYPE(HD44840, hd44840_device, "hd44840", "Hitachi HD44840") // CMOS
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//DEFINE_DEVICE_TYPE(HD44848, hd44848_device, "hd44848", "Hitachi HD44848") // CMOS, low-power
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DEFINE_DEVICE_TYPE(HD44840, hd44840_device, "hd44840", "Hitachi HD44840") // CMOS
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DEFINE_DEVICE_TYPE(HD44848, hd44848_device, "hd44848", "Hitachi HD44848") // CMOS, low-power
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// HMCS47A/C/CL, 54 pins(QFP) or 64 pins(DIP), 44 I/O lines, 4096x10 ROM, 256x4 RAM
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//DEFINE_DEVICE_TYPE(HD38870, hd38870_device, "hd38870", "Hitachi HD38870") // PMOS
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//DEFINE_DEVICE_TYPE(HD44860, hd44860_device, "hd44860", "Hitachi HD44860") // CMOS
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//DEFINE_DEVICE_TYPE(HD44868, hd44868_device, "hd44868", "Hitachi HD44868") // CMOS, low-power
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DEFINE_DEVICE_TYPE(HD38870, hd38870_device, "hd38870", "Hitachi HD38870") // PMOS
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DEFINE_DEVICE_TYPE(HD44860, hd44860_device, "hd44860", "Hitachi HD44860") // CMOS
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DEFINE_DEVICE_TYPE(HD44868, hd44868_device, "hd44868", "Hitachi HD44868") // CMOS, low-power
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// LCD-III, 64 pins, HMCS44C core, LCDC with 4 commons and 32 segments
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//DEFINE_DEVICE_TYPE(HD44790, hd44790_device, "hd44790", "Hitachi HD44790") // CMOS
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//DEFINE_DEVICE_TYPE(HD44795, hd44795_device, "hd44795", "Hitachi HD44795") // CMOS, low-power
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// LCD-IV, 64 pins, HMCS46C core, LCDC with 4 commons and 32 segments
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//DEFINE_DEVICE_TYPE(HD613901, hd613901_device, "hd613901", "Hitachi HD613901") // CMOS
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//-------------------------------------------------
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@ -139,6 +146,33 @@ hd44828_device::hd44828_device(const machine_config &mconfig, const char *tag, d
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{ }
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hmcs46_cpu_device::hmcs46_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u16 polarity) :
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hmcs40_cpu_device(mconfig, type, tag, owner, clock, HMCS46_FAMILY, polarity, 4, 12, 12, address_map_constructor(FUNC(hmcs46_cpu_device::program_2k), this), 8, address_map_constructor(FUNC(hmcs46_cpu_device::data_256x4), this))
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{ }
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hd44840_device::hd44840_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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hmcs46_cpu_device(mconfig, HD44840, tag, owner, clock, IS_CMOS)
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{ }
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hd44848_device::hd44848_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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hmcs46_cpu_device(mconfig, HD44848, tag, owner, clock, IS_CMOS)
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{ }
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hmcs47_cpu_device::hmcs47_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u16 polarity) :
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hmcs40_cpu_device(mconfig, type, tag, owner, clock, HMCS47_FAMILY, polarity, 4, 12, 12, address_map_constructor(FUNC(hmcs47_cpu_device::program_2k), this), 8, address_map_constructor(FUNC(hmcs47_cpu_device::data_256x4), this))
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{ }
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hd38870_device::hd38870_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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hmcs47_cpu_device(mconfig, HD38870, tag, owner, clock, IS_PMOS)
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{ }
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hd44860_device::hd44860_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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hmcs47_cpu_device(mconfig, HD44860, tag, owner, clock, IS_CMOS)
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{ }
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hd44868_device::hd44868_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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hmcs47_cpu_device(mconfig, HD44868, tag, owner, clock, IS_CMOS)
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{ }
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//-------------------------------------------------
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// initialization
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//-------------------------------------------------
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@ -163,7 +197,7 @@ void hmcs40_cpu_device::device_start()
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m_pc = 0;
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m_prev_pc = 0;
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m_page = 0;
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m_pc_upper = 0;
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m_a = 0;
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m_b = 0;
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m_x = 0;
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@ -195,7 +229,7 @@ void hmcs40_cpu_device::device_start()
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save_item(NAME(m_pc));
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save_item(NAME(m_prev_pc));
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save_item(NAME(m_page));
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save_item(NAME(m_pc_upper));
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save_item(NAME(m_a));
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save_item(NAME(m_b));
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save_item(NAME(m_x));
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@ -249,6 +283,10 @@ void hmcs40_cpu_device::device_reset()
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// all I/O ports set to input
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reset_io();
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// HMCS46/47 R70 set to 1 (already the default on CMOS devices)
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if (m_family == HMCS46_FAMILY || m_family == HMCS47_FAMILY)
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m_r[7] |= 1;
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}
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@ -281,10 +319,19 @@ std::unique_ptr<util::disasm_interface> hmcs40_cpu_device::create_disassembler()
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// internal memory maps
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//-------------------------------------------------
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// On HMCS42/3/4/5, only half of the ROM address range contains user-executable code,
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// there is up to 128 bytes of pattern data in the 2nd half. The 2nd half also includes
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// a couple of pages with factory test code by Hitachi, only executable when MCU test
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// mode is enabled externally. This data can still be accessed with the P opcode.
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/*
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On HMCS42/43/44/45, only half of the ROM address range contains user-executable
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code, there is up to 128 bytes of pattern data in the 2nd half. The 2nd half
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also includes a couple of pages with factory test code by Hitachi, only executable
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when MCU test mode is enabled externally (TEST pin). This data can still be accessed
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with the P opcode.
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On HMCS46/47, the 2nd half can be jumped to with a bank bit from R70. These MCUs
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have 2 more banks with factory test code, but that part of the ROM is only accessible
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under MCU test mode.
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*/
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void hmcs40_cpu_device::program_1k(address_map &map)
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{
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@ -310,6 +357,11 @@ void hmcs40_cpu_device::data_160x4(address_map &map)
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map(0xc0, 0xcf).ram().mirror(0x30);
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}
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void hmcs40_cpu_device::data_256x4(address_map &map)
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{
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map(0x00, 0xff).ram();
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}
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device_memory_interface::space_config_vector hmcs40_cpu_device::memory_space_config() const
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{
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return space_config_vector {
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@ -453,6 +505,44 @@ void hmcs45_cpu_device::write_r(u8 index, u8 data)
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logerror("ineffective write to port R%d = $%X @ $%04X\n", index, data & 0xf, m_prev_pc);
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}
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// HMCS46:
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// R0-R3 are i/o, R4,R5,R7 are extra registers, no R6
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// D0-D15 are i/o
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u8 hmcs46_cpu_device::read_r(u8 index)
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{
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index &= 7;
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if (index == 6)
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logerror("read from unknown port R%d @ $%04X\n", index, m_prev_pc);
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs46_cpu_device::write_r(u8 index, u8 data)
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{
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index &= 7;
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if (index != 6)
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hmcs40_cpu_device::write_r(index, data);
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else
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logerror("ineffective write to port R%d = $%X @ $%04X\n", index, data & 0xf, m_prev_pc);
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}
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// HMCS47:
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// R0-R5 are i/o, R6 is output-only, R7 is an extra register
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// D0-D15 are i/o
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u8 hmcs47_cpu_device::read_r(u8 index)
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{
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index &= 7;
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if (index == 6)
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logerror("read from output port R%d @ $%04X\n", index, m_prev_pc);
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return hmcs40_cpu_device::read_r(index);
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}
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//-------------------------------------------------
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// interrupt/timer
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@ -506,23 +596,13 @@ void hmcs40_cpu_device::execute_set_input(int line, int state)
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// clock tc if it is in counter mode
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if (m_cf && line == 1)
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increment_tc();
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clock_timer();
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}
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m_int[line] = state;
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}
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void hmcs40_cpu_device::cycle()
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{
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m_icount--;
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m_prescaler = (m_prescaler + 1) & 0x3f;
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// timer prescaler overflow
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if (m_prescaler == 0 && !m_cf)
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increment_tc();
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}
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void hmcs40_cpu_device::increment_tc()
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void hmcs40_cpu_device::clock_timer()
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{
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// increment timer/counter
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m_tc = (m_tc + 1) & 0xf;
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@ -535,6 +615,15 @@ void hmcs40_cpu_device::increment_tc()
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}
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}
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void hmcs40_cpu_device::clock_prescaler()
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{
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m_prescaler = (m_prescaler + 1) & 0x3f;
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// timer prescaler overflow
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if (m_prescaler == 0 && !m_cf)
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clock_timer();
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}
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//-------------------------------------------------
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// execute
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@ -555,6 +644,12 @@ inline void hmcs40_cpu_device::increment_pc()
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m_pc = (m_pc & ~mask) | ((m_pc << 1 | fb) & mask);
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}
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void hmcs40_cpu_device::cycle()
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{
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m_icount--;
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clock_prescaler();
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}
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void hmcs40_cpu_device::execute_run()
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{
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// in HLT state, the internal clock is not running
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@ -568,7 +663,7 @@ void hmcs40_cpu_device::execute_run()
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{
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// LPU is handled 1 cycle later
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if ((m_prev_op & 0x7e0) == 0x340)
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m_pc = ((m_page << 6) | (m_pc & 0x3f)) & m_pcmask;
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m_pc = ((m_pc_upper << 6) | (m_pc & 0x3f)) & m_pcmask;
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// remember previous state
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m_prev_op = m_op;
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@ -127,8 +127,9 @@ protected:
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// memory maps
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void program_1k(address_map &map);
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void program_2k(address_map &map);
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void data_160x4(address_map &map);
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void data_80x4(address_map &map);
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void data_160x4(address_map &map);
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void data_256x4(address_map &map);
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address_space_config m_program_config;
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address_space_config m_data_config;
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@ -159,7 +160,7 @@ protected:
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u16 m_pc; // program counter
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u16 m_prev_pc;
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u8 m_page; // LPU prepared page
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u8 m_pc_upper; // LPU prepared upper bits of PC
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u8 m_a; // 4-bit accumulator
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u8 m_b; // 4-bit B register
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u8 m_x; // 1/3/4-bit X register
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@ -188,6 +189,7 @@ protected:
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// misc internal helpers
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void increment_pc();
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void cycle();
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u8 ram_r();
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void ram_w(u8 data);
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@ -200,9 +202,9 @@ protected:
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virtual int read_d(u8 index);
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virtual void write_d(u8 index, int state);
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void cycle();
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void increment_tc();
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void take_interrupt();
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void clock_timer();
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void clock_prescaler();
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// opcode handlers
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void op_illegal();
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@ -409,6 +411,57 @@ public:
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};
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class hmcs46_cpu_device : public hmcs40_cpu_device
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{
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protected:
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hmcs46_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u16 polarity);
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// overrides
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virtual u8 read_r(u8 index) override;
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virtual void write_r(u8 index, u8 data) override;
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};
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class hd44840_device : public hmcs46_cpu_device
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{
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public:
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hd44840_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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class hd44848_device : public hmcs46_cpu_device
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{
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public:
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hd44848_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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class hmcs47_cpu_device : public hmcs40_cpu_device
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{
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protected:
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hmcs47_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u16 polarity);
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// overrides
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virtual u8 read_r(u8 index) override;
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};
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class hd38870_device : public hmcs47_cpu_device
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{
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public:
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hd38870_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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class hd44860_device : public hmcs47_cpu_device
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{
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public:
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hd44860_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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class hd44868_device : public hmcs47_cpu_device
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{
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public:
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hd44868_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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DECLARE_DEVICE_TYPE(HD38750, hd38750_device)
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DECLARE_DEVICE_TYPE(HD38755, hd38755_device)
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DECLARE_DEVICE_TYPE(HD44750, hd44750_device)
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@ -424,4 +477,12 @@ DECLARE_DEVICE_TYPE(HD38825, hd38825_device)
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DECLARE_DEVICE_TYPE(HD44820, hd44820_device)
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DECLARE_DEVICE_TYPE(HD44828, hd44828_device)
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DECLARE_DEVICE_TYPE(HD44840, hd44840_device)
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DECLARE_DEVICE_TYPE(HD44848, hd44848_device)
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DECLARE_DEVICE_TYPE(HD38870, hd38870_device)
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DECLARE_DEVICE_TYPE(HD44860, hd44860_device)
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DECLARE_DEVICE_TYPE(HD44868, hd44868_device)
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#endif // MAME_CPU_HMCS40_HMCS40_H
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@ -18,8 +18,9 @@ public:
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virtual ~hmcs40_disassembler();
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virtual u32 opcode_alignment() const override { return 1; }
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virtual u32 interface_flags() const override { return NONLINEAR_PC | PAGED; }
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virtual u32 interface_flags() const override { return NONLINEAR_PC | PAGED2LEVEL; }
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virtual u32 page_address_bits() const override { return 6; }
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virtual u32 page2_address_bits() const override { return 5; }
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virtual offs_t pc_linear_to_real(offs_t pc) const override { return (pc & ~0x3f) | m_l2r[pc & 0x3f]; }
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virtual offs_t pc_real_to_linear(offs_t pc) const override { return (pc & ~0x3f) | m_r2l[pc & 0x3f]; }
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virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override;
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@ -465,7 +465,11 @@ void hmcs40_cpu_device::op_lpu()
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if (m_s)
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{
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m_block_int = true;
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m_page = m_op & 0x1f;
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m_pc_upper = m_op & 0x1f;
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// on HMCS46/47, also latches bank from R70
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if (m_family == HMCS46_FAMILY || m_family == HMCS47_FAMILY)
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m_pc_upper |= ~m_r[7] << 5 & 0x20;
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}
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else
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m_op |= 0x400; // indicate unhandled LPU
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