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https://github.com/mamedev/mame.git
synced 2024-11-16 07:48:32 +01:00
rx01_cpu: Add the other flags, with a somewhat awkward display (nw)
This commit is contained in:
AJR
parent
c55bc974be
commit
962a05c2a1
3 changed files with 141 additions and 12 deletions
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@ -51,7 +51,9 @@ rx01_cpu_device::rx01_cpu_device(const machine_config &mconfig, const char *tag,
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, m_spar(0)
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, m_bar(0)
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, m_crc(0)
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, m_flag(false)
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, m_flags(0)
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, m_unit(false)
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, m_load_head(false)
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, m_icount(0)
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{
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m_inst_config.m_is_octal = true;
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@ -87,6 +89,7 @@ void rx01_cpu_device::device_start()
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state_add(RX01_PC, "PC", m_pc).mask(07777).formatstr("%04O");
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state_add(STATE_GENPC, "GENPC", m_pc).mask(07777).formatstr("%04O").noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_pc).mask(07777).formatstr("%04O").noshow();
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state_add(STATE_GENFLAGS, "FLAGS", m_flags).formatstr("%12s").noshow();
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state_add(RX01_CNTR, "CNTR", m_cntr).formatstr("%03O");
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state_add(RX01_SR, "SR", m_sr).formatstr("%03O");
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state_add(RX01_SPAR, "SPAR", m_spar).mask(15).formatstr("%3s");
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@ -95,6 +98,8 @@ void rx01_cpu_device::device_start()
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state_add(RX01_R0 + r, string_format("R%d", r).c_str(), sp[r]).formatstr("%03O");
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state_add(RX01_BAR, "BAR", m_bar).mask(07777).formatstr("%04O");
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state_add(RX01_CRC, "CRC", m_crc).formatstr("%06O");
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state_add(RX01_UNIT, "UNIT", m_unit);
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state_add(RX01_LDHD, "LDHD", m_load_head);
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// Save state registration
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save_item(NAME(m_pc));
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@ -108,7 +113,9 @@ void rx01_cpu_device::device_start()
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save_item(NAME(m_spar));
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save_item(NAME(m_bar));
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save_item(NAME(m_crc));
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save_item(NAME(m_flag));
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save_item(NAME(m_flags));
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save_item(NAME(m_unit));
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save_item(NAME(m_load_head));
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}
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void rx01_cpu_device::device_reset()
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@ -122,7 +129,9 @@ void rx01_cpu_device::device_reset()
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m_cntr = 0;
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m_sr = 0;
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m_spar = 0;
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m_flag = false;
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m_flags = 0;
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m_unit = false;
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m_load_head = false;
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}
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u8 rx01_cpu_device::mux_out()
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@ -143,23 +152,37 @@ bool rx01_cpu_device::test_condition()
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{
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switch (m_mb & 074)
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{
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case 000:
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// Interface transfer request or command pending (TODO)
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return false;
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case 004:
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// Output buffer bit 3
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return (m_flags & FF_IOB3) != 0;
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case 020:
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// MSB of shift register
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return BIT(m_sr, 7);
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case 024:
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// Counter overflow
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return m_cntr == 0377;
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case 030:
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// 16th stage of CRC generator
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return BIT(m_crc, 0);
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case 054:
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// Separated data equals MSB of shift register
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return BIT(m_sr, 7) == sep_data();
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case 060:
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// Sector buffer address overflow
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return m_bar == 07777;
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case 074:
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return m_flag;
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// Flag state equals one
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return (m_flags & FF_FLAG) != 0;
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default:
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LOG("%04o: Unhandled branch condition %d\n", m_ppc, (m_mb & 074) >> 2);
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@ -176,6 +199,14 @@ void rx01_cpu_device::shift_crc(bool data)
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m_crc = (m_crc >> 1) | 0100000;
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}
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void rx01_cpu_device::set_flag(bool j, bool k)
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{
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if (j && !(m_flags & FF_FLAG))
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m_flags |= FF_FLAG;
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else if (k && (m_flags & FF_FLAG))
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m_flags &= ~FF_FLAG;
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}
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void rx01_cpu_device::execute_run()
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{
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while (m_icount > 0)
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@ -224,6 +255,63 @@ void rx01_cpu_device::execute_run()
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}
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else switch (m_mb & 074)
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{
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case 000:
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if (BIT(m_mb, 1))
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m_flags |= FF_IOB0;
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else
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m_flags &= ~FF_IOB0;
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break;
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case 004:
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if (BIT(m_mb, 1))
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m_flags |= FF_IOB1;
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else
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m_flags &= ~FF_IOB1;
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break;
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case 010:
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if (BIT(m_mb, 1))
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m_flags |= FF_IOB2;
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else
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m_flags &= ~FF_IOB2;
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break;
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case 014:
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if (BIT(m_mb, 1))
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m_flags |= FF_IOB3;
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else
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m_flags &= ~FF_IOB3;
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break;
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case 020:
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if (BIT(m_mb, 1))
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m_flags |= FF_IOB4;
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else
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m_flags &= ~FF_IOB4;
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break;
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case 024:
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if (BIT(m_mb, 1))
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m_flags |= FF_IOB5;
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else
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m_flags &= ~FF_IOB5;
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break;
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case 030:
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if (BIT(m_mb, 1))
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m_flags |= FF_IOB6;
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else
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m_flags &= ~FF_IOB6;
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break;
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case 034:
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m_unit = BIT(m_mb, 1);
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break;
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case 040:
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m_load_head = BIT(m_mb, 1);
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break;
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case 044:
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if (BIT(m_mb, 1))
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m_bar = (m_bar + 1) & 07777;
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@ -231,6 +319,13 @@ void rx01_cpu_device::execute_run()
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m_bar = BIT(m_mb, 0) ? 0 : 06000;
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break;
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case 050:
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if (BIT(m_mb, 0))
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m_flags |= FF_WRTBUF;
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else
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m_flags &= ~FF_WRTBUF;
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break;
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case 054:
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if ((m_mb & 3) == 3)
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m_crc = 0177777;
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@ -241,7 +336,7 @@ void rx01_cpu_device::execute_run()
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break;
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case 060:
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m_flag = (!BIT(m_mb, 0) && m_flag) || (BIT(m_mb, 1) && !m_flag);
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set_flag(BIT(m_mb, 1), BIT(m_mb, 0));
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break;
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case 064:
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@ -264,10 +359,6 @@ void rx01_cpu_device::execute_run()
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else
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m_sr = (m_sr << 1) | BIT(m_mb, 1);
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break;
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default:
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LOG("%04o: Unimplemented instruction %03o\n", m_ppc, m_mb);
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break;
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}
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}
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@ -279,6 +370,28 @@ void rx01_cpu_device::state_string_export(const device_state_entry &entry, std::
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{
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switch (entry.index())
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{
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case STATE_GENFLAGS:
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if (m_flags & FF_IOB0)
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str = string_format("D%c%c%c%c%c%c %4s",
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(m_flags & FF_WRTBUF) ? 'B' : ':',
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(m_flags & FF_IOB1) ? 'W' : '.',
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(m_flags & FF_IOB2) ? 'S' : '.',
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(m_flags & FF_IOB3) ? 'H' : '.',
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(m_flags & FF_IOB4) ? 'E' : '.',
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(m_flags & FF_IOB5) ? 'T' : '.',
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(m_flags & FF_FLAG) ? ((m_flags & FF_IOB1) ? "DATA" : "FLAG") : "");
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else
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str = string_format("I%c%c%c%c%c%c %s %c",
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(m_flags & FF_WRTBUF) ? 'B' : ':',
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(m_flags & FF_IOB1) ? 'E' : '.',
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(m_flags & FF_IOB2) ? 'R' : '.',
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(m_flags & FF_IOB3) ? 'O' : '.',
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(m_flags & FF_IOB4) ? 'D' : '.',
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(m_flags & FF_IOB5) ? 'S' : '.',
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(m_flags & FF_IOB6) ? "SB" : "SR",
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(m_flags & FF_FLAG) ? 'F' : ' ');
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break;
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case RX01_SPAR:
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str = string_format("R%-2d", m_spar);
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break;
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@ -15,7 +15,20 @@ public:
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RX01_R0, RX01_R1, RX01_R2, RX01_R3, RX01_R4, RX01_R5, RX01_R6, RX01_R7,
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RX01_R8, RX01_R9, RX01_R10, RX01_R11, RX01_R12, RX01_R13, RX01_R14, RX01_R15,
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RX01_BAR,
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RX01_CRC
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RX01_CRC,
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RX01_UNIT, RX01_LDHD
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};
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enum : u16 {
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FF_IOB0 = 1 << 0,
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FF_IOB1 = 1 << 1,
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FF_IOB2 = 1 << 2,
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FF_IOB3 = 1 << 3,
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FF_IOB4 = 1 << 4,
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FF_IOB5 = 1 << 5,
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FF_IOB6 = 1 << 6,
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FF_WRTBUF = 1 << 7,
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FF_FLAG = 1 << 8
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};
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// device type constructor
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@ -48,6 +61,7 @@ private:
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bool sep_data();
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bool test_condition();
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void shift_crc(bool data);
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void set_flag(bool j, bool k);
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// address spaces
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address_space_config m_inst_config;
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@ -67,7 +81,9 @@ private:
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u8 m_spar;
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u16 m_bar;
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u16 m_crc;
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bool m_flag;
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u16 m_flags;
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bool m_unit;
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bool m_load_head;
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s32 m_icount;
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};
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@ -21,7 +21,7 @@ const char *const rx01_disassembler::s_0_or_1[2] = {
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const char *const rx01_disassembler::s_conditions[16] = {
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"RUN",
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"IOB3DT",
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"IOB3OT",
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"DATAIN",
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"INDX",
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"SR7",
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