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cop400.c: Modernized cpu core (nw)
This commit is contained in:
Wilbert Pol
parent
daf291e96f
commit
9048c5daf1
10 changed files with 1140 additions and 1323 deletions
File diff suppressed because it is too large
Load diff
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@ -95,61 +95,364 @@ enum cop400_microbus {
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COP400_MICROBUS_ENABLED
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};
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/* interface */
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struct cop400_interface
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#define MCFG_COP400_CONFIG(_cki, _cko, _microbus) \
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cop400_cpu_device::set_cki(*device, _cki); \
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cop400_cpu_device::set_cko(*device, _cko); \
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cop400_cpu_device::set_microbus(*device, _microbus);
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class cop400_cpu_device : public cpu_device
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{
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cop400_cki_bond cki; /* CKI bonding option */
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cop400_cko_bond cko; /* CKO bonding option */
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cop400_microbus microbus; /* microbus option */
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public:
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// construction/destruction
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cop400_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, UINT8 program_addr_bits, UINT8 data_addr_bits, UINT8 featuremask, UINT8 g_mask, UINT8 d_mask, UINT8 in_mask, bool has_counter, bool has_inil, address_map_constructor internal_map_program, address_map_constructor internal_map_data);
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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static void set_cki(device_t &device, cop400_cki_bond cki) { downcast<cop400_cpu_device &>(device).m_cki = cki; }
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static void set_cko(device_t &device, cop400_cko_bond cko) { downcast<cop400_cpu_device &>(device).m_cko = cko; }
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static void set_microbus(device_t &device, cop400_microbus microbus) { downcast<cop400_cpu_device &>(device).m_microbus = microbus; }
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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// device_execute_interface overrides
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virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + m_cki - 1) / m_cki; }
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virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * m_cki); }
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 2; }
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virtual UINT32 execute_input_lines() const { return 0; }
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virtual void execute_run();
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
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{
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return (spacenum == AS_PROGRAM) ? &m_program_config :
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( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
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}
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry);
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virtual void state_export(const device_state_entry &entry);
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void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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address_space_config m_program_config;
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address_space_config m_data_config;
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address_space_config m_io_config;
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cop400_cki_bond m_cki;
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cop400_cko_bond m_cko;
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cop400_microbus m_microbus;
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bool m_has_counter;
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bool m_has_inil;
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address_space *m_program;
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direct_read_data *m_direct;
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address_space *m_data;
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address_space *m_io;
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UINT8 m_featuremask;
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/* registers */
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UINT16 m_pc; /* 9/10/11-bit ROM address program counter */
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UINT16 m_prevpc; /* previous value of program counter */
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UINT8 m_a; /* 4-bit accumulator */
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UINT8 m_b; /* 5/6/7-bit RAM address register */
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int m_c; /* 1-bit carry register */
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UINT8 m_n; /* 2-bit stack pointer (COP440 only) */
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UINT8 m_en; /* 4-bit enable register */
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UINT8 m_g; /* 4-bit general purpose I/O port */
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UINT8 m_q; /* 8-bit latch for L port */
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UINT16 m_sa, m_sb, m_sc; /* subroutine save registers (not present in COP440) */
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UINT8 m_sio; /* 4-bit shift register and counter */
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int m_skl; /* 1-bit latch for SK output */
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UINT8 m_h; /* 4-bit general purpose I/O port (COP440 only) */
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UINT8 m_r; /* 8-bit general purpose I/O port (COP440 only) */
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UINT8 m_flags; // used for I/O only
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/* counter */
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UINT8 m_t; /* 8-bit timer */
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int m_skt_latch; /* timer overflow latch */
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/* input/output ports */
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UINT8 m_g_mask; /* G port mask */
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UINT8 m_d_mask; /* D port mask */
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UINT8 m_in_mask; /* IN port mask */
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UINT8 m_il; /* IN latch */
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UINT8 m_in[4]; /* IN port shift register */
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UINT8 m_si; /* serial input */
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/* skipping logic */
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int m_skip; /* skip next instruction */
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int m_skip_lbi; /* skip until next non-LBI instruction */
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int m_last_skip; /* last value of skip */
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int m_halt; /* halt mode */
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int m_idle; /* idle mode */
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/* microbus */
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int m_microbus_int; /* microbus interrupt */
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/* execution logic */
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int m_InstLen[256]; /* instruction length in bytes */
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int m_LBIops[256];
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int m_LBIops33[256];
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int m_icount; /* instruction counter */
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/* timers */
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emu_timer *m_serial_timer;
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emu_timer *m_counter_timer;
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emu_timer *m_inil_timer;
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emu_timer *m_microbus_timer;
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typedef void ( cop400_cpu_device::*cop400_opcode_func ) (UINT8 opcode);
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/* The opcode table now is a combination of cycle counts and function pointers */
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struct cop400_opcode_map {
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UINT32 cycles;
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cop400_opcode_func function;
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};
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const cop400_opcode_map *m_opcode_map;
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static const cop400_opcode_map COP410_OPCODE_23_MAP[];
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static const cop400_opcode_map COP410_OPCODE_33_MAP[];
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static const cop400_opcode_map COP410_OPCODE_MAP[];
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static const cop400_opcode_map COP420_OPCODE_23_MAP[];
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static const cop400_opcode_map COP420_OPCODE_33_MAP[];
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static const cop400_opcode_map COP420_OPCODE_MAP[];
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static const cop400_opcode_map COP444_OPCODE_23_MAP[256];
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static const cop400_opcode_map COP444_OPCODE_33_MAP[256];
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static const cop400_opcode_map COP444_OPCODE_MAP[256];
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void serial_tick();
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void counter_tick();
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void inil_tick();
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void microbus_tick();
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void PUSH(UINT16 data);
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void POP();
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void WRITE_Q(UINT8 data);
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void WRITE_G(UINT8 data);
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void illegal(UINT8 opcode);
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void asc(UINT8 opcode);
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void add(UINT8 opcode);
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void aisc(UINT8 opcode);
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void clra(UINT8 opcode);
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void comp(UINT8 opcode);
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void nop(UINT8 opcode);
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void rc(UINT8 opcode);
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void sc(UINT8 opcode);
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void xor_(UINT8 opcode);
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void adt(UINT8 opcode);
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void casc(UINT8 opcode);
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void jid(UINT8 opcode);
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void jmp(UINT8 opcode);
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void jp(UINT8 opcode);
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void jsr(UINT8 opcode);
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void ret(UINT8 opcode);
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void cop420_ret(UINT8 opcode);
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void retsk(UINT8 opcode);
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void halt(UINT8 opcode);
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void it(UINT8 opcode);
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void camq(UINT8 opcode);
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void ld(UINT8 opcode);
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void lqid(UINT8 opcode);
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void rmb0(UINT8 opcode);
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void rmb1(UINT8 opcode);
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void rmb2(UINT8 opcode);
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void rmb3(UINT8 opcode);
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void smb0(UINT8 opcode);
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void smb1(UINT8 opcode);
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void smb2(UINT8 opcode);
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void smb3(UINT8 opcode);
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void stii(UINT8 opcode);
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void x(UINT8 opcode);
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void xad(UINT8 opcode);
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void xds(UINT8 opcode);
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void xis(UINT8 opcode);
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void cqma(UINT8 opcode);
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void ldd(UINT8 opcode);
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void camt(UINT8 opcode);
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void ctma(UINT8 opcode);
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void cab(UINT8 opcode);
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void cba(UINT8 opcode);
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void lbi(UINT8 opcode);
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void lei(UINT8 opcode);
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void xabr(UINT8 opcode);
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void cop444_xabr(UINT8 opcode);
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void skc(UINT8 opcode);
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void ske(UINT8 opcode);
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void skgz(UINT8 opcode);
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void skgbz0(UINT8 opcode);
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void skgbz1(UINT8 opcode);
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void skgbz2(UINT8 opcode);
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void skgbz3(UINT8 opcode);
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void skmbz0(UINT8 opcode);
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void skmbz1(UINT8 opcode);
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void skmbz2(UINT8 opcode);
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void skmbz3(UINT8 opcode);
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void skt(UINT8 opcode);
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void ing(UINT8 opcode);
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void inl(UINT8 opcode);
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void obd(UINT8 opcode);
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void omg(UINT8 opcode);
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void xas(UINT8 opcode);
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void inin(UINT8 opcode);
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void cop402m_inin(UINT8 opcode);
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void inil(UINT8 opcode);
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void ogi(UINT8 opcode);
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void cop410_op23(UINT8 opcode);
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void cop410_op33(UINT8 opcode);
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void cop420_op23(UINT8 opcode);
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void cop420_op33(UINT8 opcode);
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void cop444_op23(UINT8 opcode);
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void cop444_op33(UINT8 opcode);
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void skgbz(int bit);
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void skmbz(int bit);
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};
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#define COP400_INTERFACE(name) const cop400_interface (name) =
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/***************************************************************************
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MACROS
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***************************************************************************/
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#define CPU_COP401 CPU_GET_INFO_NAME( cop401 )
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#define CPU_COP410 CPU_GET_INFO_NAME( cop410 )
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#define CPU_COP411 CPU_GET_INFO_NAME( cop411 )
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#define CPU_COP402 CPU_GET_INFO_NAME( cop402 )
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#define CPU_COP420 CPU_GET_INFO_NAME( cop420 )
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#define CPU_COP421 CPU_GET_INFO_NAME( cop421 )
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#define CPU_COP422 CPU_GET_INFO_NAME( cop422 )
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#define CPU_COP404 CPU_GET_INFO_NAME( cop404 )
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#define CPU_COP424 CPU_GET_INFO_NAME( cop424 )
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#define CPU_COP425 CPU_GET_INFO_NAME( cop425 )
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#define CPU_COP426 CPU_GET_INFO_NAME( cop426 )
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#define CPU_COP444 CPU_GET_INFO_NAME( cop444 )
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#define CPU_COP445 CPU_GET_INFO_NAME( cop445 )
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/***************************************************************************
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FUNCTION PROTOTYPES
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***************************************************************************/
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/* COP410 family */
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DECLARE_LEGACY_CPU_DEVICE(COP401, cop401);
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DECLARE_LEGACY_CPU_DEVICE(COP410, cop410);
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DECLARE_LEGACY_CPU_DEVICE(COP411, cop411);
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// COP401 is a ROMless version of the COP410
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class cop401_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop401_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cop410_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop410_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// COP411 is a 20-pin package version of the COP410, missing D2/D3/G3/CKO
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class cop411_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop411_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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/* COP420 family */
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DECLARE_LEGACY_CPU_DEVICE(COP402, cop402);
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DECLARE_LEGACY_CPU_DEVICE(COP420, cop420);
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DECLARE_LEGACY_CPU_DEVICE(COP421, cop421);
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DECLARE_LEGACY_CPU_DEVICE(COP422, cop422);
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// COP402 is a ROMless version of the COP420
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class cop402_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop402_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cop420_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop420_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// COP421 is a 24-pin package version of the COP420, lacking the IN ports
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class cop421_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop421_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// COP422 is a 20-pin package version of the COP420, lacking G0/G1, D0/D1, and the IN ports
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class cop422_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop422_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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/* COP444 family */
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DECLARE_LEGACY_CPU_DEVICE(COP404, cop404);
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DECLARE_LEGACY_CPU_DEVICE(COP424, cop424);
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DECLARE_LEGACY_CPU_DEVICE(COP425, cop425);
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DECLARE_LEGACY_CPU_DEVICE(COP426, cop426);
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DECLARE_LEGACY_CPU_DEVICE(COP444, cop444);
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DECLARE_LEGACY_CPU_DEVICE(COP445, cop445);
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// COP404 is a ROMless version of the COP444, which can emulate a COP410C/COP411C, COP424C/COP425C, or a COP444C/COP445C
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class cop404_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop404_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// COP424 is functionally equivalent to COP444, with only 1K ROM and 64x4 bytes RAM
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class cop424_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop424_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// COP425 is a 24-pin package version of the COP424, lacking the IN ports
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class cop425_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop425_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// COP426 is a 20-pin package version of the COP424, with only L0-L7, G2-G3, D2-D3 ports
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class cop426_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop426_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cop444_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop444_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// COP445 is a 24-pin package version of the COP444, lacking the IN ports
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class cop445_cpu_device : public cop400_cpu_device
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{
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public:
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// construction/destruction
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cop445_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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extern const device_type COP401;
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extern const device_type COP410;
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extern const device_type COP411;
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extern const device_type COP402;
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extern const device_type COP420;
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extern const device_type COP421;
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extern const device_type COP422;
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extern const device_type COP404;
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extern const device_type COP424;
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extern const device_type COP425;
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extern const device_type COP426;
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extern const device_type COP444;
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extern const device_type COP445;
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/* disassemblers */
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extern CPU_DISASSEMBLE( cop410 );
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extern CPU_DISASSEMBLE( cop420 );
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extern CPU_DISASSEMBLE( cop444 );
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#endif /* __COP400__ */
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@ -36,7 +36,7 @@ INSTRUCTION( asc )
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if (A > 0xF)
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{
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C = 1;
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cpustate->skip = 1;
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m_skip = 1;
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A &= 0xF;
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}
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else
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@ -87,7 +87,7 @@ INSTRUCTION( aisc )
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if (A > 0x0f)
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{
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cpustate->skip = 1;
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m_skip = 1;
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A &= 0xF;
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}
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}
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@ -239,7 +239,7 @@ INSTRUCTION( casc )
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if (A > 0xF)
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{
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C = 1;
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cpustate->skip = 1;
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m_skip = 1;
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A &= 0xF;
|
||||
}
|
||||
else
|
||||
|
|
@ -330,7 +330,7 @@ INSTRUCTION( jp )
|
|||
{
|
||||
// JSRP
|
||||
UINT8 a = opcode & 0x3f;
|
||||
PUSH(cpustate, PC);
|
||||
PUSH(PC);
|
||||
PC = 0x80 | a;
|
||||
}
|
||||
}
|
||||
|
|
@ -354,7 +354,7 @@ INSTRUCTION( jsr )
|
|||
{
|
||||
UINT16 a = ((opcode & 0x07) << 8) | ROM(PC);
|
||||
|
||||
PUSH(cpustate, PC + 1);
|
||||
PUSH(PC + 1);
|
||||
PC = a;
|
||||
}
|
||||
|
||||
|
|
@ -373,7 +373,7 @@ INSTRUCTION( jsr )
|
|||
|
||||
INSTRUCTION( ret )
|
||||
{
|
||||
POP(cpustate);
|
||||
POP();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -393,8 +393,8 @@ INSTRUCTION( ret )
|
|||
|
||||
INSTRUCTION( cop420_ret )
|
||||
{
|
||||
POP(cpustate);
|
||||
cpustate->skip = cpustate->last_skip;
|
||||
POP();
|
||||
m_skip = m_last_skip;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -414,8 +414,8 @@ INSTRUCTION( cop420_ret )
|
|||
|
||||
INSTRUCTION( retsk )
|
||||
{
|
||||
POP(cpustate);
|
||||
cpustate->skip = 1;
|
||||
POP();
|
||||
m_skip = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -433,7 +433,7 @@ INSTRUCTION( retsk )
|
|||
|
||||
INSTRUCTION( halt )
|
||||
{
|
||||
cpustate->halt = 1;
|
||||
m_halt = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -449,8 +449,8 @@ INSTRUCTION( halt )
|
|||
|
||||
INSTRUCTION( it )
|
||||
{
|
||||
cpustate->halt = 1;
|
||||
cpustate->idle = 1;
|
||||
m_halt = 1;
|
||||
m_idle = 1;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
|
|
@ -506,11 +506,11 @@ INSTRUCTION( camq )
|
|||
|
||||
UINT8 data = (A << 4) | RAM_R(B);
|
||||
|
||||
WRITE_Q(cpustate, data);
|
||||
WRITE_Q(data);
|
||||
|
||||
#ifdef CAMQ_BUG
|
||||
WRITE_Q(cpustate, 0x3c);
|
||||
WRITE_Q(cpustate, data);
|
||||
WRITE_Q(0x3c);
|
||||
WRITE_Q(data);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -553,10 +553,10 @@ INSTRUCTION( ld )
|
|||
|
||||
INSTRUCTION( lqid )
|
||||
{
|
||||
PUSH(cpustate, PC);
|
||||
PUSH(PC);
|
||||
PC = (PC & 0x700) | (A << 4) | RAM_R(B);
|
||||
WRITE_Q(cpustate, ROM(PC));
|
||||
POP(cpustate);
|
||||
WRITE_Q(ROM(PC));
|
||||
POP();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -733,7 +733,7 @@ INSTRUCTION( xds )
|
|||
|
||||
B = B ^ r;
|
||||
|
||||
if (Bd == 0x0f) cpustate->skip = 1;
|
||||
if (Bd == 0x0f) m_skip = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -768,7 +768,7 @@ INSTRUCTION( xis )
|
|||
|
||||
B = B ^ r;
|
||||
|
||||
if (Bd == 0x00) cpustate->skip = 1;
|
||||
if (Bd == 0x00) m_skip = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -920,7 +920,7 @@ INSTRUCTION( lbi )
|
|||
B = (opcode & 0x70) | (((opcode & 0x0f) + 1) & 0x0f);
|
||||
}
|
||||
|
||||
cpustate->skip_lbi = 1;
|
||||
m_skip_lbi = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1014,7 +1014,7 @@ INSTRUCTION( cop444_xabr )
|
|||
|
||||
INSTRUCTION( skc )
|
||||
{
|
||||
if (C == 1) cpustate->skip = 1;
|
||||
if (C == 1) m_skip = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1032,7 +1032,7 @@ INSTRUCTION( skc )
|
|||
|
||||
INSTRUCTION( ske )
|
||||
{
|
||||
if (A == RAM_R(B)) cpustate->skip = 1;
|
||||
if (A == RAM_R(B)) m_skip = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1050,7 +1050,7 @@ INSTRUCTION( ske )
|
|||
|
||||
INSTRUCTION( skgz )
|
||||
{
|
||||
if (IN_G() == 0) cpustate->skip = 1;
|
||||
if (IN_G() == 0) m_skip = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1073,15 +1073,15 @@ INSTRUCTION( skgz )
|
|||
|
||||
*/
|
||||
|
||||
INLINE void skgbz(cop400_state *cpustate, int bit)
|
||||
void cop400_cpu_device::skgbz(int bit)
|
||||
{
|
||||
if (!BIT(IN_G(), bit)) cpustate->skip = 1;
|
||||
if (!BIT(IN_G(), bit)) m_skip = 1;
|
||||
}
|
||||
|
||||
INSTRUCTION( skgbz0 ) { skgbz(cpustate, 0); }
|
||||
INSTRUCTION( skgbz1 ) { skgbz(cpustate, 1); }
|
||||
INSTRUCTION( skgbz2 ) { skgbz(cpustate, 2); }
|
||||
INSTRUCTION( skgbz3 ) { skgbz(cpustate, 3); }
|
||||
INSTRUCTION( skgbz0 ) { skgbz(0); }
|
||||
INSTRUCTION( skgbz1 ) { skgbz(1); }
|
||||
INSTRUCTION( skgbz2 ) { skgbz(2); }
|
||||
INSTRUCTION( skgbz3 ) { skgbz(3); }
|
||||
|
||||
/*
|
||||
|
||||
|
|
@ -1103,15 +1103,15 @@ INSTRUCTION( skgbz3 ) { skgbz(cpustate, 3); }
|
|||
|
||||
*/
|
||||
|
||||
INLINE void skmbz(cop400_state *cpustate, int bit)
|
||||
void cop400_cpu_device::skmbz(int bit)
|
||||
{
|
||||
if (!BIT(RAM_R(B), bit)) cpustate->skip = 1;
|
||||
if (!BIT(RAM_R(B), bit)) m_skip = 1;
|
||||
}
|
||||
|
||||
INSTRUCTION( skmbz0 ) { skmbz(cpustate, 0); }
|
||||
INSTRUCTION( skmbz1 ) { skmbz(cpustate, 1); }
|
||||
INSTRUCTION( skmbz2 ) { skmbz(cpustate, 2); }
|
||||
INSTRUCTION( skmbz3 ) { skmbz(cpustate, 3); }
|
||||
INSTRUCTION( skmbz0 ) { skmbz(0); }
|
||||
INSTRUCTION( skmbz1 ) { skmbz(1); }
|
||||
INSTRUCTION( skmbz2 ) { skmbz(2); }
|
||||
INSTRUCTION( skmbz3 ) { skmbz(3); }
|
||||
|
||||
/*
|
||||
|
||||
|
|
@ -1128,10 +1128,10 @@ INSTRUCTION( skmbz3 ) { skmbz(cpustate, 3); }
|
|||
|
||||
INSTRUCTION( skt )
|
||||
{
|
||||
if (cpustate->skt_latch)
|
||||
if (m_skt_latch)
|
||||
{
|
||||
cpustate->skt_latch = 0;
|
||||
cpustate->skip = 1;
|
||||
m_skt_latch = 0;
|
||||
m_skip = 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1212,7 +1212,7 @@ INSTRUCTION( obd )
|
|||
|
||||
INSTRUCTION( omg )
|
||||
{
|
||||
WRITE_G(cpustate, RAM_R(B));
|
||||
WRITE_G(RAM_R(B));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1314,5 +1314,5 @@ INSTRUCTION( ogi )
|
|||
{
|
||||
UINT8 y = opcode & 0x0f;
|
||||
|
||||
WRITE_G(cpustate, y);
|
||||
WRITE_G(y);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -190,14 +190,6 @@ static CDP1852_INTERFACE( draco_cdp1852_out1_intf )
|
|||
DEVCB_NULL
|
||||
};
|
||||
|
||||
/* COP400 Interface */
|
||||
|
||||
static COP400_INTERFACE( draco_cop_intf )
|
||||
{
|
||||
COP400_CKI_DIVISOR_16, // ???
|
||||
COP400_CKO_OSCILLATOR_OUTPUT, // ???
|
||||
COP400_MICROBUS_DISABLED
|
||||
};
|
||||
|
||||
/* Memory Maps */
|
||||
|
||||
|
|
@ -518,7 +510,7 @@ static MACHINE_CONFIG_START( draco, draco_state )
|
|||
MCFG_CPU_ADD(COP402N_TAG, COP402, DRACO_SND_CHR1)
|
||||
MCFG_CPU_PROGRAM_MAP(draco_sound_map)
|
||||
MCFG_CPU_IO_MAP(draco_sound_io_map)
|
||||
MCFG_CPU_CONFIG(draco_cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_DISABLED )
|
||||
|
||||
/* input/output hardware */
|
||||
MCFG_CDP1852_ADD("ic29", CDP1852_CLOCK_HIGH, cidelsa_cdp1852_in0_intf) /* clock is really tied to CDP1876 CMSEL (pin 32) */
|
||||
|
|
|
|||
|
|
@ -622,12 +622,6 @@ static const ay8910_interface ay8910_config =
|
|||
DEVCB_NULL
|
||||
};
|
||||
|
||||
static COP400_INTERFACE( looping_cop_intf )
|
||||
{
|
||||
COP400_CKI_DIVISOR_16, // ???
|
||||
COP400_CKO_OSCILLATOR_OUTPUT, // ???
|
||||
COP400_MICROBUS_DISABLED
|
||||
};
|
||||
|
||||
/*************************************
|
||||
*
|
||||
|
|
@ -651,7 +645,7 @@ static MACHINE_CONFIG_START( looping, looping_state )
|
|||
MCFG_CPU_PROGRAM_MAP(looping_cop_map)
|
||||
MCFG_CPU_DATA_MAP(looping_cop_data_map)
|
||||
MCFG_CPU_IO_MAP(looping_cop_io_map)
|
||||
MCFG_CPU_CONFIG(looping_cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_DISABLED )
|
||||
|
||||
|
||||
/* video hardware */
|
||||
|
|
|
|||
|
|
@ -782,15 +782,6 @@ void thayers_state::machine_reset()
|
|||
// laserdisc_set_type(m_laserdisc, newtype);
|
||||
}
|
||||
|
||||
/* COP400 Interface */
|
||||
|
||||
static COP400_INTERFACE( thayers_cop_intf )
|
||||
{
|
||||
COP400_CKI_DIVISOR_4, // ???
|
||||
COP400_CKO_OSCILLATOR_OUTPUT, // ???
|
||||
COP400_MICROBUS_DISABLED
|
||||
};
|
||||
|
||||
/* Machine Driver */
|
||||
|
||||
static MACHINE_CONFIG_START( thayers, thayers_state )
|
||||
|
|
@ -801,7 +792,7 @@ static MACHINE_CONFIG_START( thayers, thayers_state )
|
|||
|
||||
MCFG_CPU_ADD("mcu", COP421, XTAL_4MHz/2) // COP421L-PCA/N
|
||||
MCFG_CPU_IO_MAP(thayers_cop_io_map)
|
||||
MCFG_CPU_CONFIG(thayers_cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_4, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_DISABLED )
|
||||
|
||||
|
||||
MCFG_LASERDISC_PR7820_ADD("laserdisc")
|
||||
|
|
|
|||
|
|
@ -62,13 +62,6 @@ INPUT_PORTS_END
|
|||
|
||||
/* Machine Driver */
|
||||
|
||||
static COP400_INTERFACE( advision_cop411_interface )
|
||||
{
|
||||
COP400_CKI_DIVISOR_4,
|
||||
COP400_CKO_RAM_POWER_SUPPLY, // ??? or not connected
|
||||
COP400_MICROBUS_DISABLED
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( advision, advision_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD(I8048_TAG, I8048, XTAL_11MHz)
|
||||
|
|
@ -76,7 +69,7 @@ static MACHINE_CONFIG_START( advision, advision_state )
|
|||
MCFG_CPU_IO_MAP(io_map)
|
||||
|
||||
MCFG_CPU_ADD(COP411_TAG, COP411, 52631*16) // COP411L-KCN/N
|
||||
MCFG_CPU_CONFIG(advision_cop411_interface)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_4, COP400_CKO_RAM_POWER_SUPPLY, COP400_MICROBUS_DISABLED )
|
||||
MCFG_CPU_IO_MAP(sound_io_map)
|
||||
|
||||
/* video hardware */
|
||||
|
|
|
|||
|
|
@ -119,13 +119,6 @@ static const floppy_interface lisa_floppy_interface =
|
|||
NULL
|
||||
};
|
||||
|
||||
static COP400_INTERFACE( cop_intf )
|
||||
{
|
||||
COP400_CKI_DIVISOR_16, // ???
|
||||
COP400_CKO_OSCILLATOR_OUTPUT,
|
||||
COP400_MICROBUS_ENABLED
|
||||
};
|
||||
|
||||
/***************************************************************************
|
||||
MACHINE DRIVER
|
||||
***************************************************************************/
|
||||
|
|
@ -139,11 +132,11 @@ static MACHINE_CONFIG_START( lisa, lisa_state )
|
|||
|
||||
MCFG_CPU_ADD(COP421_TAG, COP421, 3900000)
|
||||
MCFG_CPU_IO_MAP(lisa_cop_io_map)
|
||||
MCFG_CPU_CONFIG(cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
|
||||
|
||||
MCFG_CPU_ADD(KB_COP421_TAG, COP421, 3900000) // ?
|
||||
MCFG_CPU_IO_MAP(kb_cop_io_map)
|
||||
MCFG_CPU_CONFIG(cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
|
||||
|
||||
MCFG_CPU_ADD("fdccpu", M6504, 2000000) /* 16.000 MHz / 8 in when DIS asserted, 16.000 MHz / 9 otherwise (?) */
|
||||
MCFG_CPU_PROGRAM_MAP(lisa_fdc_map)
|
||||
|
|
|
|||
|
|
@ -1337,13 +1337,6 @@ INTERRUPT_GEN_MEMBER(newbrain_state::newbrain_interrupt)
|
|||
}
|
||||
}
|
||||
|
||||
static COP400_INTERFACE( newbrain_cop_intf )
|
||||
{
|
||||
COP400_CKI_DIVISOR_16, // ???
|
||||
COP400_CKO_OSCILLATOR_OUTPUT,
|
||||
COP400_MICROBUS_ENABLED
|
||||
};
|
||||
|
||||
/* Machine Drivers */
|
||||
|
||||
static const cassette_interface newbrain_cassette_interface =
|
||||
|
|
@ -1382,7 +1375,7 @@ static MACHINE_CONFIG_START( newbrain_a, newbrain_state )
|
|||
|
||||
MCFG_CPU_ADD(COP420_TAG, COP420, XTAL_16MHz/8) // COP420-GUW/N
|
||||
MCFG_CPU_IO_MAP(newbrain_cop_io_map)
|
||||
MCFG_CPU_CONFIG(newbrain_cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
|
||||
|
||||
MCFG_GFXDECODE(newbrain)
|
||||
|
||||
|
|
|
|||
|
|
@ -32,23 +32,16 @@ static ADDRESS_MAP_START( cop_io, AS_IO, 8, t400_test_suite_state )
|
|||
AM_RANGE(COP400_PORT_CKO, COP400_PORT_CKO) AM_NOP
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static COP400_INTERFACE( cop_intf )
|
||||
{
|
||||
COP400_CKI_DIVISOR_16,
|
||||
COP400_CKO_OSCILLATOR_OUTPUT,
|
||||
COP400_MICROBUS_ENABLED
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( test_t410, t400_test_suite_state )
|
||||
MCFG_CPU_ADD("maincpu", COP410, 1000000)
|
||||
MCFG_CPU_IO_MAP(cop_io)
|
||||
MCFG_CPU_CONFIG(cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( test_t420, t400_test_suite_state )
|
||||
MCFG_CPU_ADD("maincpu", COP420, 1000000)
|
||||
MCFG_CPU_IO_MAP(cop_io)
|
||||
MCFG_CPU_CONFIG(cop_intf)
|
||||
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START( test410 )
|
||||
|
|
|
|||
Loading…
Reference in a new issue