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h8: Make fully wait-states compatible
This commit is contained in:
Olivier Galibert
parent
78661e9aa9
commit
82c1756aa3
5 changed files with 455 additions and 415 deletions
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@ -1,6 +1,19 @@
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# license:BSD-3-Clause
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# copyright-holders:Olivier Galibert, Devin Acker
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macro prefetch_start
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NPC = PC & 0xffffff;
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PIR = read16i(PC);
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PC += 2;
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macro prefetch
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prefetch_start
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prefetch_done();
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macro prefetch_noirq
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prefetch_start
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prefetch_done_noirq();
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10000 reset
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10001 irq
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@ -12,12 +25,12 @@
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0380 fff0 0 ldbank r8l bankl g
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TMP1 = r8_r(IR[0]) & 0x3f;
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m_banknum = (m_banknum & 0xffc0) | TMP1;
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prefetch();
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prefetch
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03c0 fff0 0 ldbank r8l bankh g
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TMP1 = r8_r(IR[0]) & 0x3f;
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m_banknum = (TMP1 << 6) | (m_banknum & 0x3f);
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prefetch();
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prefetch
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0400 ff00 0 orc imm8 ccr
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0500 ff00 0 xorc imm8 ccr
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@ -26,15 +39,15 @@
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0740 ffc0 0 ldc imm6l ccr g
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CCR = IR[0] & 0x3f;
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update_irq_filter();
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prefetch_noirq();
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prefetch_noirq
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0780 ffc0 0 ldbank imm6l bankl g
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m_banknum = (m_banknum & 0xffc0) | (IR[0] & 0x3f);
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prefetch();
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prefetch
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07c0 ffc0 0 ldbank imm6l bankh g
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m_banknum = ((IR[0] & 0x3f) << 6) | (m_banknum & 0x3f);
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prefetch();
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prefetch
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0800 ff00 0 add.b r8h r8l
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0900 ff00 0 add.w r16h r16l
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@ -114,7 +127,7 @@
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internal(1);
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m_banknum = ((IR[0] & 0x3f) << 2) | (IR[1] >> 14);
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PC = 0x8000 | (IR[1] & 0x3fff);
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prefetch();
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prefetch
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5c00 ff8f 0 jsr r16h -
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5c80 ffff 0 jsr abs16e -
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@ -131,7 +144,7 @@
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67000000 ff8fff0f 0 btst r8h r16ihh
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6800 ff80 0 mov.b r16ih r8l g
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prefetch_start();
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prefetch_start
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internal(1);
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TMP1 = read8ib(r16_r(IR[0] >> 4));
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set_nzv8(TMP1);
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@ -139,7 +152,7 @@
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prefetch_done();
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6900 ff88 0 mov.w r16ih r16l g
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prefetch_start();
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prefetch_start
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internal(1);
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TMP1 = read16ib(r16_r(IR[0] >> 4));
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set_nzv16(TMP1);
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@ -148,7 +161,7 @@
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6a00 ff80 0 mov.b r16ph r8l g
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TMP2 = r16_r(IR[0] >> 4);
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prefetch_start();
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prefetch_start
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internal(2);
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TMP1 = read8ib(TMP2);
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TMP2 += 1;
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@ -159,7 +172,7 @@
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6b00 ff88 0 mov.w r16ph r16l g
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TMP2 = r16_r(IR[0] >> 4);
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prefetch_start();
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prefetch_start
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internal(2);
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TMP1 = read16ib(TMP2);
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TMP2 += 2;
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@ -172,7 +185,7 @@
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6d00 fff0 0 mov.w abs16 r16l
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6e00 ff80 0 mov.b r16d16h r8l g
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prefetch_start();
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prefetch_start
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TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]);
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internal(1);
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TMP2 = read8ib(TMP1);
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@ -181,7 +194,7 @@
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prefetch_done();
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6f00 ff80 0 mov.w r16d16h r16l g
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prefetch_start();
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prefetch_start
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TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]);
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internal(1);
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TMP2 = read16ib(TMP1);
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@ -199,7 +212,7 @@
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77000000 ff00ff0f 0 btst r8h abs8
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7800 ff80 0 mov.b r8l r16ih g
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prefetch_start();
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prefetch_start
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TMP1 = r8_r(IR[0]);
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set_nzv8(TMP1);
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internal(1);
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@ -207,7 +220,7 @@
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prefetch_done();
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7900 ff88 0 mov.w r16l r16ih g
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prefetch_start();
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prefetch_start
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TMP1 = r16_r(IR[0]);
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set_nzv16(TMP1);
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internal(1);
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@ -217,7 +230,7 @@
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7a00 ff80 0 mov.b r8l pr16h g
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TMP1 = r8_r(IR[0]);
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TMP2 = r16_r(IR[0] >> 4);
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prefetch_start();
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prefetch_start
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internal(1);
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TMP2 -= 1;
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r16_w(IR[0] >> 4, TMP2);
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@ -229,7 +242,7 @@
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7b00 ff88 0 mov.w r16l pr16h g
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TMP1 = r16_r(IR[0]);
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TMP2 = r16_r(IR[0] >> 4);
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prefetch_start();
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prefetch_start
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internal(1);
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TMP2 -= 2;
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r16_w(IR[0] >> 4, TMP2);
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@ -242,7 +255,7 @@
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7d00 fff0 0 mov.w r16l abs16
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7e00 ff80 0 mov.b r8l r16d16h g
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prefetch_start();
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prefetch_start
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TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]);
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TMP2 = r8_r(IR[0]);
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set_nzv8(TMP2);
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@ -251,7 +264,7 @@
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prefetch_done();
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7f00 ff80 0 mov.w r16l r16d16h g
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prefetch_start();
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prefetch_start
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TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]);
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TMP2 = r16_r(IR[0]);
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set_nzv16(TMP2);
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@ -46,11 +46,11 @@ void h8_device::device_start()
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uint32_t pcmask = mode_advanced ? 0xffffff : 0xffff;
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state_add<uint32_t>(H8_PC, "PC",
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[this]() { return NPC; },
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[this](uint32_t pc) { PC = PPC = NPC = pc; prefetch_noirq_notrace(); }
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[this](uint32_t pc) { PC = PPC = NPC = pc; PIR = read16i(PC); PC += 2; prefetch_done_noirq_notrace(); }
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).mask(pcmask);
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state_add<uint32_t>(STATE_GENPC, "GENPC",
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[this]() { return NPC; },
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[this](uint32_t pc) { PC = PPC = NPC = pc; prefetch_noirq_notrace(); }
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[this](uint32_t pc) { PC = PPC = NPC = pc; PIR = read16i(PC); PC += 2; prefetch_done_noirq_notrace(); }
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).mask(pcmask).noshow();
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state_add(STATE_GENPCBASE, "CURPC", PPC).mask(pcmask).noshow();
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state_add(H8_CCR, "CCR", CCR);
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@ -361,13 +361,6 @@ uint16_t h8_device::read16i(uint32_t adr)
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return cache.read_word(adr & ~1);
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}
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uint16_t h8_device::fetch()
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{
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uint16_t res = read16i(PC);
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PC += 2;
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return res;
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}
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uint8_t h8_device::read8(uint32_t adr)
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{
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icount--;
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@ -95,6 +95,7 @@ protected:
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virtual void device_reset() override;
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// device_execute_interface overrides
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virtual bool cpu_is_interruptible() const override { return true; }
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virtual uint32_t execute_min_cycles() const noexcept override;
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virtual uint32_t execute_max_cycles() const noexcept override;
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virtual uint32_t execute_input_lines() const noexcept override;
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@ -156,17 +157,11 @@ protected:
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virtual void irq_setup() = 0;
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uint16_t read16i(uint32_t adr);
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uint16_t fetch();
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inline void fetch(int slot) { IR[slot] = fetch(); }
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uint8_t read8(uint32_t adr);
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void write8(uint32_t adr, uint8_t data);
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uint16_t read16(uint32_t adr);
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void write16(uint32_t adr, uint16_t data);
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void internal(int cycles);
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inline void prefetch() { prefetch_start(); prefetch_done(); }
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inline void prefetch_noirq() { prefetch_start(); prefetch_done_noirq(); }
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inline void prefetch_noirq_notrace() { prefetch_start(); prefetch_done_noirq_notrace(); }
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void prefetch_start() { NPC = PC & 0xffffff; PIR = fetch(); }
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void prefetch_switch(uint32_t pc, uint16_t ir) { NPC = pc & 0xffffff; PC = pc+2; PIR = ir; }
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void prefetch_done();
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void prefetch_done_noirq();
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File diff suppressed because it is too large
Load diff
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@ -52,7 +52,7 @@ def hexsplit(str):
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return res
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def has_memory(ins):
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for s in ["read", "write", "sp_push", "sp_pop", "sp32_push", "sp32_pop", "fetch(", "prefetch_start(", "prefetch(", "prefetch_noirq("]:
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for s in ["read", "write"]:
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if s in ins:
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return True
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return False
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@ -68,9 +68,16 @@ def save_full_one(f, t, name, source):
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substate = 1
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for line in source:
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if has_memory(line):
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print("\tif(icount <= bcount) { inst_substate = %d; return; }" % substate, file=f)
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print(line, file=f)
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substate += 1
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print("\tif(icount <= bcount) {", file=f)
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print("\t\tif(access_to_be_redone()) {", file=f)
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print("\t\t\ticount++;", file=f)
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print("\t\t\tinst_substate = %d;" % substate, file=f)
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print("\t\t} else", file=f)
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print("\t\t\tinst_substate = %d;" % (substate+1), file=f)
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print("\t\treturn;", file=f)
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print("\t}", file=f)
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substate += 2
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elif has_eat(line):
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print("\tif(icount) { icount = bcount; } inst_substate = %d; return;" % substate, file=f)
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substate += 1
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@ -87,11 +94,20 @@ def save_partial_one(f, t, name, source):
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substate = 1
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for line in source:
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if has_memory(line):
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print("\tif(icount <= bcount) { inst_substate = %d; return; }" % substate, file=f)
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print("\t[[fallthrough]];", file=f)
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print("case %d:;" % substate, file=f)
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print(line, file=f)
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substate += 1
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print("\tif(icount <= bcount) {", file=f)
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print("\t\tif(access_to_be_redone()) {", file=f)
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print("\t\t\ticount++;", file=f)
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print("\t\t\tinst_substate = %d;" % substate, file=f)
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print("\t\t} else", file=f)
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print("\t\t\tinst_substate = %d;" % (substate+1), file=f)
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print("\t\treturn;", file=f)
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print("\t}", file=f)
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print("\t[[fallthrough]];", file=f)
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print("case %d:;" % (substate+1), file=f)
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substate += 2
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elif has_eat(line):
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print("\tif(icount) { icount = bcount; } inst_substate = %d; return;" % substate, file=f)
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print("case %d:;" % substate, file=f)
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@ -156,7 +172,8 @@ class Opcode:
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self.extra_words = extra_words
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base_offset = len(self.val)/2 + self.skip
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for i in range(0, extra_words):
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self.source.append("\tfetch(%d);\n" % (i+base_offset))
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self.source.append("\tIR[%d] = read16i(PC);" % (i+base_offset))
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self.source.append("\tPC += 2;")
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def description(self):
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return "%s %s %s" % (self.name, self.am1, self.am2)
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@ -269,7 +286,8 @@ class DispatchStep:
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end = start + self.skip
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s = []
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for i in range(start, end+1):
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s.append("\tIR[%d] = fetch();" % i)
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s.append("\tIR[%d] = read16i(PC);" % i)
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s.append("\tPC += 2;")
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s.append("\tinst_state = 0x%x0000 | IR[%d];" % (self.id, end))
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return s
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