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pci: Move interrupt line and pin functions into PCI device and add variables (nw)
pci-ide: Add legacy mapping based on prog i/f register (nw)
This commit is contained in:
Ted Green
parent
57ac19beee
commit
58ff1eb0e1
4 changed files with 105 additions and 47 deletions
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@ -14,8 +14,11 @@ ide_pci_device::ide_pci_device(const machine_config &mconfig, const char *tag, d
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}
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DEVICE_ADDRESS_MAP_START(config_map, 32, ide_pci_device)
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AM_RANGE(0x08, 0x0b) AM_WRITE8(prog_if_w, 0x0000ff00)
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AM_RANGE(0x10, 0x1f) AM_WRITE(address_base_w)
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AM_RANGE(0x40, 0x5f) AM_READWRITE(pcictrl_r, pcictrl_w)
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AM_RANGE(0x70, 0x77) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w) // PCI646
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AM_RANGE(0x78, 0x7f) AM_DEVREADWRITE("ide2", bus_master_ide_controller_device, bmdma_r, bmdma_w) // PCI646
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AM_INHERIT_FROM(pci_device::config_map)
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ADDRESS_MAP_END
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@ -80,7 +83,17 @@ void ide_pci_device::device_start()
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add_map(16, M_IO, FUNC(ide_pci_device::bus_master_map));
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bank_infos[4].adr = 0xf00;
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// Setup stored BARs
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pci_bar[0] = 0x1f0;
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pci_bar[1] = 0x3f4;
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pci_bar[2] = 0x170;
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pci_bar[3] = 0x374;
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pci_bar[4] = 0xf00;
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m_irq_handler.resolve_safe();
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intr_pin = 0x1;
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intr_line = 0xe;
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}
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void ide_pci_device::device_reset()
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@ -94,8 +107,8 @@ void ide_pci_device::device_reset()
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READ32_MEMBER(ide_pci_device::ide_read_cs1)
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{
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// PCI offset starts at 0x3f4, idectrl expects 0x3f0
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uint32_t data = 0;
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data = m_ide->read_cs1(space, ++offset, mem_mask);
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uint32_t data;
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data = m_ide->read_cs1(space, 1, mem_mask);
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if (0)
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logerror("%s:ide_read_cs1 offset=%08X data=%08X mask=%08X\n", machine().describe_context(), offset, data, mem_mask);
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return data;
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@ -104,21 +117,21 @@ READ32_MEMBER(ide_pci_device::ide_read_cs1)
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WRITE32_MEMBER(ide_pci_device::ide_write_cs1)
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{
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// PCI offset starts at 0x3f4, idectrl expects 0x3f0
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m_ide->write_cs1(space, ++offset, data, mem_mask);
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m_ide->write_cs1(space, 1, data, mem_mask);
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}
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READ32_MEMBER(ide_pci_device::ide2_read_cs1)
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{
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// PCI offset starts at 0x374, idectrl expects 0x370
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uint32_t data = 0;
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data = m_ide2->read_cs1(space, ++offset, mem_mask);
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uint32_t data;
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data = m_ide2->read_cs1(space, 1, mem_mask);
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return data;
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}
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WRITE32_MEMBER(ide_pci_device::ide2_write_cs1)
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{
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// PCI offset starts at 0x374, idectrl expects 0x370
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m_ide2->write_cs1(space, ++offset, data, mem_mask);
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m_ide2->write_cs1(space, 1, data, mem_mask);
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}
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WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
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@ -141,6 +154,42 @@ WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
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logerror("%s:ide_interrupt %i set to %i\n", machine().describe_context(), m_irq_num, state);
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}
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WRITE8_MEMBER(ide_pci_device::prog_if_w)
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{
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uint32_t oldVal = pclass;
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pclass = (pclass & ~(0xff)) | (data & 0xff);
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// Check for switch to/from compatibility (legacy) mode from/to pci mode
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if ((oldVal ^ pclass) & 0x5) {
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// Map Primary IDE Channel
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if (pclass & 0x1) {
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// PCI Mode
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// Enabling BAR 4 in legacy mode
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bank_infos[4].flags &= ~M_DISABLED;
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pci_device::address_base_w(space, 0, pci_bar[0]);
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pci_device::address_base_w(space, 1, pci_bar[1]);
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} else {
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// Legacy Mode
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// Disabling BAR 4 in legacy mode
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bank_infos[4].flags |= M_DISABLED;
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pci_device::address_base_w(space, 0, 0x1f0);
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pci_device::address_base_w(space, 1, 0x3f4);
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}
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// Map Primary IDE Channel
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if (pclass & 0x4) {
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// PCI Mode
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pci_device::address_base_w(space, 2, pci_bar[2]);
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pci_device::address_base_w(space, 3, pci_bar[3]);
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}
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else {
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// Legacy Mode
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pci_device::address_base_w(space, 2, 0x170);
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pci_device::address_base_w(space, 3, 0x374);
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}
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}
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if (1)
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logerror("%s:prog_if_w pclass = %06X\n", machine().describe_context(), pclass);
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}
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READ32_MEMBER(ide_pci_device::pcictrl_r)
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{
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return m_config_data[offset];
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@ -150,7 +199,7 @@ WRITE32_MEMBER(ide_pci_device::pcictrl_w)
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{
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COMBINE_DATA(&m_config_data[offset]);
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// PCI646U2 Offset 0x50 is interrupt status
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if (main_id == 0x10950646 && offset == 0x10 / 4 && (data & 0x4)) {
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if (main_id == 0x10950646 && offset == (0x10 / 4) && (data & 0x4)) {
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m_config_data[0x10 / 4] &= ~0x4;
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if (0)
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logerror("%s:ide_pci_device::pcictrl_w Clearing interrupt status\n", machine().describe_context());
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@ -161,24 +210,24 @@ WRITE32_MEMBER(ide_pci_device::address_base_w)
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{
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// data==0xffffffff is used to identify required memory space
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if (data != 0xffffffff) {
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// Bits 0 (ide) and 2 (ide2) control if the mapping is legacy or BAR
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// Save local copy of BAR
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pci_bar[offset] = data;
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// Bits 0 (primary) and 2 (secondary) control if the mapping is legacy or BAR
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switch (offset) {
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case 0:
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if ((pclass & 0x1) == 0)
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data = (data & 0xfffff000) | 0x1f0;
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case 0: case 1:
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if ((pclass & 0x1) == 1)
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pci_device::address_base_w(space, offset, data);
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break;
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case 1:
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if ((pclass & 0x1) == 0)
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data = (data & 0xfffff000) | 0x3f4;
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break;
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case 2:
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if ((pclass & 0x4) == 0)
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data = (data & 0xfffff000) | 0x170;
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case 2: case 3:
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if ((pclass & 0x4) == 1)
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pci_device::address_base_w(space, offset, data);
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break;
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default:
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if ((pclass & 0x4) == 0)
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data = (data & 0xfffff000) | 0x374;
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pci_device::address_base_w(space, offset, data);
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// Not sure what to do for the bus master ide BAR in legacy mode
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// prog_if_w will disable register in legacy mode
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if ((pclass & 0x5) == 0)
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logerror("Mapping bar[%i] in legacy mode\n", offset);
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}
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}
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pci_device::address_base_w(space, offset, data);
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}
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@ -53,6 +53,7 @@ private:
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cpu_device *m_cpu;
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int m_irq_num;
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devcb_write_line m_irq_handler;
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uint32_t pci_bar[6];
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uint32_t m_config_data[0x10];
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DECLARE_ADDRESS_MAP(chan1_data_command_map, 32);
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@ -60,6 +61,7 @@ private:
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DECLARE_ADDRESS_MAP(chan2_data_command_map, 32);
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DECLARE_ADDRESS_MAP(chan2_control_map, 32);
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DECLARE_ADDRESS_MAP(bus_master_map, 32);
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DECLARE_WRITE8_MEMBER(prog_if_w);
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DECLARE_READ32_MEMBER(pcictrl_r);
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DECLARE_WRITE32_MEMBER(pcictrl_w);
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DECLARE_WRITE32_MEMBER(address_base_w);
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@ -23,6 +23,8 @@ DEVICE_ADDRESS_MAP_START(config_map, 32, pci_device)
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AM_RANGE(0x2c, 0x2f) AM_WRITENOP
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AM_RANGE(0x30, 0x33) AM_READWRITE (expansion_base_r, expansion_base_w)
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AM_RANGE(0x34, 0x37) AM_READ8 (capptr_r, 0x000000ff)
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AM_RANGE(0x3c, 0x3f) AM_READWRITE8(interrupt_line_r, interrupt_line_w, 0x000000ff)
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AM_RANGE(0x3c, 0x3f) AM_READWRITE8(interrupt_pin_r, interrupt_pin_w, 0x0000ff00)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(config_map, 32, pci_bridge_device)
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@ -67,6 +69,8 @@ pci_device::pci_device(const machine_config &mconfig, device_type type, const ch
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pclass = 0xffffff;
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subsystem_id = 0xffffffff;
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is_multifunction_device = false;
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intr_pin = 0x0;
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intr_line = 0xff;
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}
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void pci_device::set_ids(uint32_t _main_id, uint8_t _revision, uint32_t _pclass, uint32_t _subsystem_id)
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@ -245,6 +249,30 @@ READ8_MEMBER(pci_device::capptr_r)
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return 0x00;
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}
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READ8_MEMBER(pci_device::interrupt_line_r)
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{
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logerror("interrupt_line_r = %02x\n", intr_line);
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return intr_line;
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}
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WRITE8_MEMBER(pci_device::interrupt_line_w)
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{
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COMBINE_DATA(&intr_line);
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logerror("interrupt_line_w %02x\n", data);
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}
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READ8_MEMBER(pci_device::interrupt_pin_r)
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{
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logerror("interrupt_pin_r = %02x\n", intr_pin);
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return intr_pin;
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}
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WRITE8_MEMBER(pci_device::interrupt_pin_w)
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{
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COMBINE_DATA(&intr_pin);
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logerror("interrupt_pin_w = %02x\n", data);
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}
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void pci_device::set_remap_cb(mapper_cb _remap_cb)
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{
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remap_cb = _remap_cb;
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@ -749,28 +777,6 @@ WRITE16_MEMBER(pci_bridge_device::iolimitu_w)
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logerror("iolimitu_w %04x\n", iolimitu);
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}
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READ8_MEMBER (pci_bridge_device::interrupt_line_r)
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{
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logerror("interrupt_line_r\n");
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return 0xff;
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}
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WRITE8_MEMBER (pci_bridge_device::interrupt_line_w)
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{
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logerror("interrupt_line_w %02x\n", data);
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}
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READ8_MEMBER (pci_bridge_device::interrupt_pin_r)
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{
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logerror("interrupt_pin_r\n");
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return 0xff;
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}
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WRITE8_MEMBER (pci_bridge_device::interrupt_pin_w)
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{
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logerror("interrupt_pin_w %02x\n", data);
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}
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READ16_MEMBER (pci_bridge_device::bridge_control_r)
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{
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return bridge_control;
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@ -80,6 +80,10 @@ public:
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DECLARE_READ32_MEMBER (expansion_base_r);
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DECLARE_WRITE32_MEMBER(expansion_base_w);
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virtual DECLARE_READ8_MEMBER(capptr_r);
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DECLARE_READ8_MEMBER(interrupt_line_r);
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DECLARE_WRITE8_MEMBER(interrupt_line_w);
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DECLARE_READ8_MEMBER(interrupt_pin_r);
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DECLARE_WRITE8_MEMBER(interrupt_pin_w);
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protected:
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optional_memory_region m_region;
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@ -118,6 +122,7 @@ protected:
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uint32_t expansion_rom_size;
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uint32_t expansion_rom_base;
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bool is_multifunction_device;
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uint8_t intr_line, intr_pin;
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virtual void device_start() override;
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virtual void device_reset() override;
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@ -192,10 +197,6 @@ public:
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DECLARE_WRITE16_MEMBER(iobaseu_w);
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DECLARE_READ16_MEMBER (iolimitu_r);
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DECLARE_WRITE16_MEMBER(iolimitu_w);
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DECLARE_READ8_MEMBER (interrupt_line_r);
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DECLARE_WRITE8_MEMBER (interrupt_line_w);
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DECLARE_READ8_MEMBER (interrupt_pin_r);
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DECLARE_WRITE8_MEMBER (interrupt_pin_w);
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DECLARE_READ16_MEMBER (bridge_control_r);
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DECLARE_WRITE16_MEMBER(bridge_control_w);
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