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mmd2.cpp: that was a lot of run-time tag map lookups... (nw)
This commit is contained in:
Vas Crabb
parent
83123f2334
commit
58a2d5859a
1 changed files with 88 additions and 78 deletions
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@ -5,7 +5,7 @@
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MMD-2 driver by Miodrag Milanovic
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2009-05-12 Initial version
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2011-01-12 MMD2 working {Robbbert]
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2011-01-12 MMD2 working [Robbbert]
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http://www.cs.unc.edu/~yakowenk/classiccmp/mmd2/
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@ -106,9 +106,15 @@ public:
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_cass(*this, "cassette")
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, m_banks(*this, "bank%u", 1U)
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, m_io_keyboard(*this, "X%u", 0)
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, m_io_dsw(*this, "DSW")
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, m_digits(*this, "digit%u", 0U)
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{ }
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, m_p(*this, "p%u_%u", 0U, 0U)
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, m_led_halt(*this, "led_halt")
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, m_led_hold(*this, "led_hold")
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, m_led_inte(*this, "led_inte")
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{ }
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void mmd2(machine_config &config);
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@ -116,6 +122,10 @@ public:
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DECLARE_INPUT_CHANGED_MEMBER(reset_button);
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protected:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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private:
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DECLARE_WRITE8_MEMBER(port00_w);
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DECLARE_WRITE8_MEMBER(port01_w);
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@ -133,51 +143,56 @@ private:
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DECLARE_WRITE_LINE_MEMBER(so);
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void io_map(address_map &map);
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void mem_map(address_map &map);
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virtual void machine_reset() override;
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void reset_banks();
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uint8_t m_digit;
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virtual void machine_start() override { m_digits.resolve(); }
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required_device<i8080_cpu_device> m_maincpu;
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required_device<cassette_image_device> m_cass;
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required_memory_bank_array<8> m_banks;
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required_ioport_array<4> m_io_keyboard;
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required_ioport m_io_dsw;
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output_finder<9> m_digits;
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output_finder<3, 8> m_p;
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output_finder<> m_led_halt;
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output_finder<> m_led_hold;
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output_finder<> m_led_inte;
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};
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WRITE8_MEMBER( mmd2_state::port00_w )
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{
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output().set_value("p0_7", BIT(data,7) ? 0 : 1);
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output().set_value("p0_6", BIT(data,6) ? 0 : 1);
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output().set_value("p0_5", BIT(data,5) ? 0 : 1);
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output().set_value("p0_4", BIT(data,4) ? 0 : 1);
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output().set_value("p0_3", BIT(data,3) ? 0 : 1);
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output().set_value("p0_2", BIT(data,2) ? 0 : 1);
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output().set_value("p0_1", BIT(data,1) ? 0 : 1);
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output().set_value("p0_0", BIT(data,0) ? 0 : 1);
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m_p[0][7] = BIT(data,7) ? 0 : 1;
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m_p[0][6] = BIT(data,6) ? 0 : 1;
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m_p[0][5] = BIT(data,5) ? 0 : 1;
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m_p[0][4] = BIT(data,4) ? 0 : 1;
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m_p[0][3] = BIT(data,3) ? 0 : 1;
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m_p[0][2] = BIT(data,2) ? 0 : 1;
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m_p[0][1] = BIT(data,1) ? 0 : 1;
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m_p[0][0] = BIT(data,0) ? 0 : 1;
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}
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WRITE8_MEMBER( mmd2_state::port01_w )
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{
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output().set_value("p1_7", BIT(data,7) ? 0 : 1);
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output().set_value("p1_6", BIT(data,6) ? 0 : 1);
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output().set_value("p1_5", BIT(data,5) ? 0 : 1);
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output().set_value("p1_4", BIT(data,4) ? 0 : 1);
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output().set_value("p1_3", BIT(data,3) ? 0 : 1);
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output().set_value("p1_2", BIT(data,2) ? 0 : 1);
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output().set_value("p1_1", BIT(data,1) ? 0 : 1);
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output().set_value("p1_0", BIT(data,0) ? 0 : 1);
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m_p[1][7] = BIT(data,7) ? 0 : 1;
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m_p[1][6] = BIT(data,6) ? 0 : 1;
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m_p[1][5] = BIT(data,5) ? 0 : 1;
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m_p[1][4] = BIT(data,4) ? 0 : 1;
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m_p[1][3] = BIT(data,3) ? 0 : 1;
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m_p[1][2] = BIT(data,2) ? 0 : 1;
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m_p[1][1] = BIT(data,1) ? 0 : 1;
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m_p[1][0] = BIT(data,0) ? 0 : 1;
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}
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WRITE8_MEMBER( mmd2_state::port02_w )
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{
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output().set_value("p2_7", BIT(data,7) ? 0 : 1);
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output().set_value("p2_6", BIT(data,6) ? 0 : 1);
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output().set_value("p2_5", BIT(data,5) ? 0 : 1);
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output().set_value("p2_4", BIT(data,4) ? 0 : 1);
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output().set_value("p2_3", BIT(data,3) ? 0 : 1);
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output().set_value("p2_2", BIT(data,2) ? 0 : 1);
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output().set_value("p2_1", BIT(data,1) ? 0 : 1);
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output().set_value("p2_0", BIT(data,0) ? 0 : 1);
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m_p[2][7] = BIT(data,7) ? 0 : 1;
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m_p[2][6] = BIT(data,6) ? 0 : 1;
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m_p[2][5] = BIT(data,5) ? 0 : 1;
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m_p[2][4] = BIT(data,4) ? 0 : 1;
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m_p[2][3] = BIT(data,3) ? 0 : 1;
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m_p[2][2] = BIT(data,2) ? 0 : 1;
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m_p[2][1] = BIT(data,1) ? 0 : 1;
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m_p[2][0] = BIT(data,0) ? 0 : 1;
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}
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void mmd2_state::mem_map(address_map &map)
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@ -276,22 +291,16 @@ C D E F MEM REGS AUX CANCEL
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READ8_MEMBER( mmd2_state::bank_r )
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{
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membank("bank1")->set_entry(offset);
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membank("bank2")->set_entry(offset);
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membank("bank3")->set_entry(offset);
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membank("bank4")->set_entry(offset);
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membank("bank5")->set_entry(offset);
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membank("bank6")->set_entry(offset);
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membank("bank7")->set_entry(offset);
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membank("bank8")->set_entry(offset);
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return 0xff;
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for (auto &bank : m_banks)
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bank->set_entry(offset);
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return space.unmap();
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}
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READ8_MEMBER( mmd2_state::port01_r )
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{
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// need to add ttyin bit 0
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uint8_t data = 0x84;
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data |= ioport("DSW")->read();
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data |= m_io_dsw->read();
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data |= (m_cass->input() < 0.02) ? 0 : 2;
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return data;
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}
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@ -326,16 +335,25 @@ READ8_MEMBER( mmd2_state::keyboard_r )
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WRITE8_MEMBER( mmd2_state::status_callback )
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{
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// operate the HALT LED
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output().set_value("led_halt", ~data & i8080_cpu_device::STATUS_HLTA);
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m_led_halt = ~data & i8080_cpu_device::STATUS_HLTA;
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// operate the HOLD LED - this should connect to the HLDA pin,
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// but it isn't emulated, using WO instead (whatever that does).
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output().set_value("led_hold", data & i8080_cpu_device::STATUS_WO);
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m_led_hold = data & i8080_cpu_device::STATUS_WO;
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}
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WRITE_LINE_MEMBER( mmd2_state::inte_callback )
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{
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// operate the INTE LED
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output().set_value("led_inte", state);
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m_led_inte = state;
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}
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void mmd2_state::machine_start()
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{
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m_digits.resolve();
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m_p.resolve();
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m_led_halt.resolve();
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m_led_hold.resolve();
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m_led_inte.resolve();
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}
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void mmd2_state::machine_reset()
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@ -345,47 +363,39 @@ void mmd2_state::machine_reset()
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void mmd2_state::reset_banks()
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{
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membank("bank1")->set_entry(0);
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membank("bank2")->set_entry(0);
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membank("bank3")->set_entry(0);
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membank("bank4")->set_entry(0);
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membank("bank5")->set_entry(0);
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membank("bank6")->set_entry(0);
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membank("bank7")->set_entry(0);
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membank("bank8")->set_entry(0);
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for (auto &bank : m_banks)
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bank->set_entry(0);
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}
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void mmd2_state::init_mmd2()
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{
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/*
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We preset all banks here, so that bankswitching will incur no speed penalty.
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0000/0400 indicate ROMs, D800/DC00/E400 indicate RAM, 8000 is a dummy write area for ROM banks.
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*/
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uint8_t *p_ram = memregion("maincpu")->base();
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membank("bank1")->configure_entry(0, &p_ram[0x0000]);
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membank("bank1")->configure_entry(1, &p_ram[0xd800]);
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membank("bank1")->configure_entry(2, &p_ram[0x0c00]);
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membank("bank2")->configure_entry(0, &p_ram[0x8000]);
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membank("bank2")->configure_entry(1, &p_ram[0xd800]);
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membank("bank2")->configure_entry(2, &p_ram[0x8000]);
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membank("bank3")->configure_entry(0, &p_ram[0x0400]);
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membank("bank3")->configure_entry(1, &p_ram[0xdc00]);
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membank("bank3")->configure_entry(2, &p_ram[0xdc00]);
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membank("bank4")->configure_entry(0, &p_ram[0x8000]);
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membank("bank4")->configure_entry(1, &p_ram[0xdc00]);
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membank("bank4")->configure_entry(2, &p_ram[0xdc00]);
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membank("bank5")->configure_entry(0, &p_ram[0xd800]);
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membank("bank5")->configure_entry(1, &p_ram[0x0000]);
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membank("bank5")->configure_entry(2, &p_ram[0x0000]);
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membank("bank6")->configure_entry(0, &p_ram[0xd800]);
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membank("bank6")->configure_entry(1, &p_ram[0x8000]);
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membank("bank6")->configure_entry(2, &p_ram[0x8000]);
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membank("bank7")->configure_entry(0, &p_ram[0xe400]);
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membank("bank7")->configure_entry(1, &p_ram[0x0c00]);
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membank("bank7")->configure_entry(2, &p_ram[0xd800]);
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membank("bank8")->configure_entry(0, &p_ram[0xe400]);
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membank("bank8")->configure_entry(1, &p_ram[0x8000]);
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membank("bank8")->configure_entry(2, &p_ram[0xd800]);
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// We preset all banks here, so that bankswitching will incur no speed penalty.
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// 0000/0400 indicate ROMs, D800/DC00/E400 indicate RAM, 8000 is a dummy write area for ROM banks.
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uint8_t *const p_ram = memregion("maincpu")->base();
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m_banks[0]->configure_entry(0, &p_ram[0x0000]);
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m_banks[0]->configure_entry(1, &p_ram[0xd800]);
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m_banks[0]->configure_entry(2, &p_ram[0x0c00]);
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m_banks[1]->configure_entry(0, &p_ram[0x8000]);
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m_banks[1]->configure_entry(1, &p_ram[0xd800]);
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m_banks[1]->configure_entry(2, &p_ram[0x8000]);
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m_banks[2]->configure_entry(0, &p_ram[0x0400]);
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m_banks[2]->configure_entry(1, &p_ram[0xdc00]);
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m_banks[2]->configure_entry(2, &p_ram[0xdc00]);
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m_banks[3]->configure_entry(0, &p_ram[0x8000]);
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m_banks[3]->configure_entry(1, &p_ram[0xdc00]);
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m_banks[3]->configure_entry(2, &p_ram[0xdc00]);
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m_banks[4]->configure_entry(0, &p_ram[0xd800]);
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m_banks[4]->configure_entry(1, &p_ram[0x0000]);
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m_banks[4]->configure_entry(2, &p_ram[0x0000]);
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m_banks[5]->configure_entry(0, &p_ram[0xd800]);
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m_banks[5]->configure_entry(1, &p_ram[0x8000]);
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m_banks[5]->configure_entry(2, &p_ram[0x8000]);
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m_banks[6]->configure_entry(0, &p_ram[0xe400]);
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m_banks[6]->configure_entry(1, &p_ram[0x0c00]);
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m_banks[6]->configure_entry(2, &p_ram[0xd800]);
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m_banks[7]->configure_entry(0, &p_ram[0xe400]);
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m_banks[7]->configure_entry(1, &p_ram[0x8000]);
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m_banks[7]->configure_entry(2, &p_ram[0xd800]);
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}
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void mmd2_state::mmd2(machine_config &config)
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