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Added kidniki sound board netlist to nl_examples. Currently the netlist
boils down to a 87x87 matrix. This is due to a total of 6 opamps which all are submodels and thus add their own internal nets. Gauss Seidel iterative solving comes to it's limits. nltool runs this at about 50% speed on my machine. Given the complexity this is quite good. Yet, any m62 game currently will not be playable. Time for a new cpu :-) [Andrew Gardner, Couriersud]
This commit is contained in:
couriersud
parent
5107c16ca6
commit
3db351f5c9
2 changed files with 392 additions and 3 deletions
381
nl_examples/kidniki.c
Normal file
381
nl_examples/kidniki.c
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@ -0,0 +1,381 @@
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#include "netlist/devices/net_lib.h"
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#include "netlist/analog/nld_bjt.h"
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NETLIST_START(dummy)
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// EESCHEMA NETLIST VERSION 1.1 (SPICE FORMAT) CREATION DATE: SAT 06 JUN 2015 01:06:26 PM CEST
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// TO EXCLUDE A COMPONENT FROM THE SPICE NETLIST ADD [SPICE_NETLIST_ENABLED] USER FIELD SET TO: N
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// TO REORDER THE COMPONENT SPICE NODE SEQUENCE ADD [SPICE_NODE_SEQUENCE] USER FIELD AND DEFINE SEQUENCE: 2,1,0
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// SHEET NAME:/
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// IGNORED O_AUDIO0: O_AUDIO0 49 0
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// .END
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SOLVER(Solver, 12000)
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PARAM(Solver.ACCURACY, 1e-7)
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PARAM(Solver.NR_LOOPS, 50)
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PARAM(Solver.GS_LOOPS, 4)
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PARAM(Solver.SOR_FACTOR, 1.0)
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#if 0
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PARAM(Solver.SOR_FACTOR, 1)
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PARAM(Solver.DYNAMIC_TS, 1)
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PARAM(Solver.LTE, 1e1)
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#endif
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//FIXME proper models!
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NET_MODEL(".model 2SC945 NPN(Is=2.04f Xti=3 Eg=1.11 Vaf=6 Bf=400 Ikf=20m Xtb=1.5 Br=3.377 Rc=1 Cjc=1p Mjc=.3333 Vjc=.75 Fc=.5 Cje=25p Mje=.3333 Vje=.75 Tr=450n Tf=20n Itf=0 Vtf=0 Xtf=0 VCEO=45V ICrating=150M MFG=Toshiba)")
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NET_MODEL(".model 1S1588 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
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//NET_C(R44.1, XU1.7)
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/*
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* Workaround: The simplified opamp model does not correctly
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* model the internals of the inputs.
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*/
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ANALOG_INPUT(VWORKAROUND, 1.821)
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RES(RWORKAROUND, RES_K(27))
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NET_C(VWORKAROUND.Q, RWORKAROUND.1)
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NET_C(XU1.6, RWORKAROUND.2)
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ANALOG_INPUT(I_V5, 5)
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//ANALOG_INPUT(I_V0, 0)
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ALIAS(I_V0.Q, GND)
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#if 0
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ANALOG_INPUT(I_SD0, 0)
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ANALOG_INPUT(I_BD0, 0)
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ANALOG_INPUT(I_CH0, 0)
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ANALOG_INPUT(I_OH0, 0)
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ANALOG_INPUT(I_SOUNDIC0, 0)
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ANALOG_INPUT(I_OKI0, 0)
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ANALOG_INPUT(I_SOUND0, 0)
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ANALOG_INPUT(I_SINH0, 0)
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#else
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TTL_INPUT(I_SD0, 1)
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TTL_INPUT(I_BD0, 1)
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//TTL_INPUT(I_CH0, 1)
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CLOCK(I_CH0, 50)
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TTL_INPUT(I_OH0, 1)
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TTL_INPUT(I_SOUNDIC0, 1)
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ANALOG_INPUT(I_OKI0, 0)
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TTL_INPUT(I_SOUND0, 1)
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TTL_INPUT(I_SINH0, 1)
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#endif
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RES(R95, RES_K(330))
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TTL_7404_DIP(XU3)
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CAP(C69, CAP_N(10))
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RES(R96, RES_K(150))
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RES(R103, RES_K(470))
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CAP(C73, CAP_N(10))
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RES(R102, RES_K(150))
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RES(R105, RES_K(470))
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CAP(C72, CAP_N(12))
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RES(R106, RES_K(150))
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RES(R108, RES_K(560))
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CAP(C77, CAP_N(12))
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RES(R107, RES_K(150))
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RES(R100, RES_K(560))
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CAP(C67, CAP_N(15))
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RES(R101, RES_K(150))
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RES(R98, RES_K(650))
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CAP(C68, CAP_N(15))
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RES(R97, RES_K(150))
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RES(R65, RES_K(1))
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CAP(C63, CAP_N(1))
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RES(R65_1, RES_K(27))
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RES(R30, RES_K(10))
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RES(R44, RES_K(100))
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CAP(C38, CAP_N(1))
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CAP(C39, CAP_N(1))
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RES(R38, 820)
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CAP(C40, CAP_P(12))
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SUBMODEL(LM324_DIP,XU1)
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RES(R48_2, RES_K(100))
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CAP(C45, CAP_N(22))
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RES(R54, RES_K(680))
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RES(R55, RES_K(510))
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RES(R45, RES_K(1))
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CAP(C44, CAP_U(1))
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RES(R66, RES_M(1))
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QBJT_EB(Q4, "2SC945")
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RES(R70, RES_K(10))
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RES(R63, RES_K(1))
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RES(R69, RES_K(1))
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CAP(C49, CAP_N(3.3))
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CAP(C42, CAP_N(1.2))
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RES(R58, RES_K(39))
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RES(R57, 560)
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CAP(C47, CAP_U(1))
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QBJT_EB(Q6, "2SC945")
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CAP(C50, CAP_N(22))
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RES(R72, RES_K(100))
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RES(R67, RES_K(100))
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RES(R61, RES_K(100))
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CAP(C51, CAP_N(22))
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RES(R71, RES_K(100))
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RES(R68, RES_K(100))
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RES(R62, RES_K(100))
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QBJT_EB(Q5, "2SC945")
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RES(R60, RES_K(39))
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RES(R59, 560)
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CAP(C48, CAP_U(1))
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CAP(C43, CAP_N(1.2))
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RES(R46, RES_K(12))
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CAP(C35, CAP_N(1))
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CAP(C34, CAP_N(1))
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RES(R39, RES_K(22))
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RES(R41, RES_K(10))
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RES(R32, RES_K(4.7))
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CAP(C31, CAP_N(470))
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RES(R40, RES_K(10))
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RES(R27, RES_K(6.8))
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CAP(C28, CAP_U(1))
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RES(R28, RES_K(150))
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RES(R29, RES_K(2.7))
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RES(R31, RES_K(5.1))
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RES(R42, RES_K(150))
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RES(R51, RES_K(150))
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CAP(C36, CAP_N(6.5))
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CAP(C32, CAP_N(3.3))
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CAP(C41, CAP_U(1))
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RES(R43, 470)
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SUBMODEL(LM358_DIP,XU2)
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RES(R50, RES_K(22))
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CAP(C56, CAP_N(6.8))
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RES(R75, RES_K(10))
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RES(R74, RES_K(10))
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CAP(C53, CAP_N(27))
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CAP(C52, CAP_N(27))
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RES(R73, RES_K(10))
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RES(R76, RES_K(10))
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RES(R78, RES_K(3.3))
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RES(R77, RES_K(2.2))
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CAP(C58, CAP_U(47))
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RES(R49, RES_K(10))
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RES(R48, 470)
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QBJT_EB(Q9, "2SC945")
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QBJT_EB(Q10, "2SC945")
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RES(R84, RES_K(1))
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CAP(C61, CAP_N(22))
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CAP(C60, CAP_N(22))
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RES(R87, RES_K(68))
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RES(R86, RES_K(10))
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RES(R93, RES_K(1))
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RES(R85, RES_M(2.2))
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CAP(C64, CAP_N(68))
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CAP(C65, CAP_N(68))
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CAP(C66, CAP_N(68))
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CAP(C76, CAP_N(68))
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RES(R94, RES_K(22))
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RES(R119, RES_K(22))
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RES(R104, RES_K(22))
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RES(R53, RES_K(100))
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RES(R34, RES_K(100))
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RES(R52, RES_K(100))
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CAP(C37, CAP_N(22))
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RES(R83, RES_K(12))
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RES(R81, 220)
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RES(R82, RES_M(2.2))
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RES(R92, RES_K(22))
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RES(R89, RES_K(22))
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CAP(C62, CAP_N(6.8))
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CAP(C57, CAP_N(6.8))
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CAP(C59, CAP_N(6.8))
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RES(R90, RES_K(390))
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CAP(C33, CAP_U(1))
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RES(R37, RES_K(47))
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QBJT_EB(Q3, "2SC945")
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RES(R35, RES_K(100))
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RES(R36, RES_K(100))
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RES(R91, RES_K(100))
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CAP(C70, CAP_N(22))
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DIODE(D4, "1S1588")
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DIODE(D5, "1S1588")
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DIODE(D3, "1S1588")
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POT(RV1, RES_K(50))
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QBJT_EB(Q7, "2SC945")
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NET_C(R95.1, XU3.2, R96.2)
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NET_C(R95.2, XU3.1, C69.1)
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NET_C(XU3.3, R103.2, C73.1)
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NET_C(XU3.4, R103.1, R102.2)
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NET_C(XU3.5, R105.2, C72.1)
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NET_C(XU3.6, R105.1, R106.2)
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NET_C(/*XU3.7,*/ C69.2, C73.2, C72.2, C77.2, C67.2, C68.2, R65.2, R38.2, XU1.11, R54.2, Q4.E, R63.2, C47.2, R72.2, R67.2, R71.2, R68.2, C48.2, R46.2, C28.1, C32.1, R43.2, XU2.4, C56.1, C52.1, R77.2, C58.1, R48.2, R93.2, R94.2, R119.2, R104.2, R53.2, R34.2, R81.2, R92.2, R89.2, C33.1, R37.2, R36.1, R91.1, I_V0.Q, RV1.3)
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NET_C(XU3.8, R108.1, R107.2)
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NET_C(XU3.9, R108.2, C77.1)
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NET_C(XU3.10, R100.1, R101.2)
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NET_C(XU3.11, R100.2, C67.1)
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NET_C(XU3.12, R98.1, R97.2)
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NET_C(XU3.13, R98.2, C68.1)
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NET_C(/*XU3.14,*/ XU1.4, R66.1, R70.1, Q6.C, Q5.C, XU2.8, R78.1, R86.1, R83.1, Q3.C, I_V5.Q)
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NET_C(R96.1, R102.1, R106.1, R107.1, R101.1, R97.1, R65.1, C63.2)
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NET_C(C63.1, R65_1.2)
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NET_C(R65_1.1, R44.2, C38.2, C40.2, XU1.6)
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NET_C(R30.1, R41.1, R40.1, R76.2, R78.2, R77.1, C58.2)
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NET_C(R30.2, XU1.5)
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NET_C(R44.1, C39.1, C40.1, R48_2.2)
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NET_C(C38.1, C39.2, R38.1)
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NET_C(XU1.1, XU1.2, R39.1, R32.2)
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NET_C(XU1.3, C34.1, R41.2)
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NET_C(XU1.7, R45.2)
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NET_C(XU1.8, XU1.9, R31.2, C36.2)
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NET_C(XU1.10, R42.1, C32.2)
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NET_C(XU1.12, C49.1, C31.1, R40.2, C61.1, C60.1)
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NET_C(XU1.13, R27.1, R28.2)
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NET_C(XU1.14, R28.1, R29.2, I_SINH0.Q)
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NET_C(R48_2.1, C45.2, R54.1)
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NET_C(C45.1, R55.1, Q7.B)
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NET_C(R55.2, R90.2, C33.2, R37.1, Q3.E)
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NET_C(R45.1, C44.2)
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NET_C(C44.1, R66.2, Q4.B)
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NET_C(Q4.C, C42.1, C43.1, R46.1, C35.2, D4.K, D5.K)
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NET_C(R70.2, R69.2, Q7.C)
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NET_C(R63.1, Q7.E)
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NET_C(R69.1, C49.2)
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NET_C(C42.2, R58.1, D5.A)
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NET_C(R58.2, R57.1, C47.1)
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NET_C(R57.2, Q6.E)
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NET_C(Q6.B, R61.1)
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NET_C(C50.1, R67.1, R61.2)
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NET_C(C50.2, R72.1, I_OH0.Q)
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NET_C(C51.1, R68.1, R62.2)
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NET_C(C51.2, R71.1, I_CH0.Q)
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NET_C(R62.1, Q5.B)
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NET_C(Q5.E, R59.2)
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NET_C(R60.1, C43.2, D4.A)
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NET_C(R60.2, R59.1, C48.1)
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NET_C(C35.1, C34.2, R39.2)
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NET_C(R32.1, C31.2)
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NET_C(R27.2, C28.2)
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NET_C(R29.1, R31.1, R50.2, R49.1, RV1.1)
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NET_C(R42.2, R51.1, C36.1)
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NET_C(R51.2, C41.1)
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NET_C(C41.2, R43.1, I_SOUNDIC0.Q)
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NET_C(XU2.1, XU2.2, R73.1)
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NET_C(XU2.3, R76.1, I_OKI0.Q)
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NET_C(XU2.5, C56.2, R75.1)
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NET_C(XU2.6, XU2.7, R50.1, C53.2)
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NET_C(R75.2, R74.1, C53.1)
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NET_C(R74.2, C52.2, R73.2)
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NET_C(R49.2, R48.1, I_SOUND0.Q)
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NET_C(Q9.E, R81.1)
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NET_C(Q9.C, R84.2, R83.2, R82.1, C59.1)
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NET_C(Q9.B, R82.2, C62.1)
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NET_C(Q10.E, R93.1)
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NET_C(Q10.C, R87.2, R86.2, R85.1, C76.1)
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NET_C(Q10.B, R85.2, C64.1)
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NET_C(R84.1, C61.2)
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NET_C(C60.2, R87.1)
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NET_C(C64.2, C65.1, R94.1, D3.K)
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NET_C(C65.2, C66.1, R119.1)
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NET_C(C66.2, C76.2, R104.1)
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NET_C(R53.1, R52.2, C37.1)
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NET_C(R34.1, C37.2, I_BD0.Q)
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NET_C(R52.1, D3.A)
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NET_C(R92.1, C62.2, C57.1)
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NET_C(R89.1, C57.2, C59.2, R90.1)
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NET_C(Q3.B, R35.1)
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NET_C(R35.2, R36.2, C70.1)
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NET_C(R91.2, C70.2, I_SD0.Q)
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NETLIST_END()
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NETLIST_START(opamp)
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/* Opamp model from
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*
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* http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
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*
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* Bandwidth 1Mhz
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*
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*/
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/* Terminal definitions for calling netlists */
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ALIAS(PLUS, G1.IP) // Positive input
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ALIAS(MINUS, G1.IN) // Negative input
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ALIAS(OUT, EBUF.OP) // Opamp output ...
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ALIAS(GND, EBUF.ON) // GND terminal
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ALIAS(VCC, DUMMY.I) // VCC terminal
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DUMMY_INPUT(DUMMY)
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/* The opamp model */
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VCCS(G1)
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PARAM(G1.RI, RES_K(1000))
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PARAM(G1.G, 100) // typical OP-AMP amplification 100 * 1000 = 100000
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RES(RP1, 1000)
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CAP(CP1, 1.59e-5) // <== change to 1.59e-3 for 10Khz bandwidth
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VCVS(EBUF)
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PARAM(EBUF.RO, 50)
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PARAM(EBUF.G, 1)
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// NET_C(EBUF.ON, GND)
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NET_C(G1.ON, GND)
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NET_C(RP1.2, GND)
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NET_C(CP1.2, GND)
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NET_C(EBUF.IN, GND)
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NET_C(RP1.1, G1.OP)
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NET_C(CP1.1, RP1.1)
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DIODE(DP,"1N914")
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DIODE(DN,"1N914")
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NET_C(DP.K, VCC)
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NET_C(DP.A, DN.K, RP1.1)
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NET_C(DN.A, GND)
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NET_C(EBUF.IP, RP1.1)
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NETLIST_END()
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NETLIST_START(LM324_DIP)
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SUBMODEL(opamp, op1)
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SUBMODEL(opamp, op2)
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SUBMODEL(opamp, op3)
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SUBMODEL(opamp, op4)
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ALIAS( 1, op1.OUT)
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ALIAS( 2, op1.MINUS)
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ALIAS( 3, op1.PLUS)
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ALIAS( 7, op2.OUT)
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ALIAS( 6, op2.MINUS)
|
||||
ALIAS( 5, op2.PLUS)
|
||||
|
||||
ALIAS( 8, op3.OUT)
|
||||
ALIAS( 9, op3.MINUS)
|
||||
ALIAS(10, op3.PLUS)
|
||||
|
||||
ALIAS(14, op4.OUT)
|
||||
ALIAS(13, op4.MINUS)
|
||||
ALIAS(12, op4.PLUS)
|
||||
|
||||
NET_C(op1.GND, op2.GND, op3.GND, op4.GND)
|
||||
NET_C(op1.VCC, op2.VCC, op3.VCC, op4.VCC)
|
||||
|
||||
ALIAS(11, op1.GND)
|
||||
ALIAS( 4, op1.VCC)
|
||||
NETLIST_END()
|
||||
|
||||
NETLIST_START(LM358_DIP)
|
||||
SUBMODEL(opamp, op1)
|
||||
SUBMODEL(opamp, op2)
|
||||
|
||||
ALIAS( 1, op1.OUT)
|
||||
ALIAS( 2, op1.MINUS)
|
||||
ALIAS( 3, op1.PLUS)
|
||||
|
||||
ALIAS( 7, op2.OUT)
|
||||
ALIAS( 6, op2.MINUS)
|
||||
ALIAS( 5, op2.PLUS)
|
||||
|
||||
|
||||
NET_C(op1.GND, op2.GND)
|
||||
NET_C(op1.VCC, op2.VCC)
|
||||
|
||||
ALIAS( 4, op1.GND)
|
||||
ALIAS( 8, op1.VCC)
|
||||
NETLIST_END()
|
||||
|
|
@ -16,14 +16,20 @@ NETLIST_START(main)
|
|||
//PARAM(Solver.CONVERG, 1.0)
|
||||
//PARAM(Solver.GS_LOOPS, 30)
|
||||
|
||||
// Tie up +5 to opamps thought it's not currently needed
|
||||
// Stay compatible
|
||||
ANALOG_INPUT(V5, 5)
|
||||
NET_C(op.VCC, V5)
|
||||
NET_C(op1.VCC, V5)
|
||||
|
||||
/* Opamp wired as impedance changer */
|
||||
SUBMODEL(op, opamp)
|
||||
SUBMODEL(opamp, op)
|
||||
|
||||
NET_C(op.GND, GND)
|
||||
NET_C(op.PLUS, clk)
|
||||
NET_C(op.MINUS, op.OUT)
|
||||
|
||||
SUBMODEL(op1, opamp)
|
||||
SUBMODEL(opamp, op1)
|
||||
/* Wired as inverting amplifier connected to output of first opamp */
|
||||
|
||||
RES(R1, 100000)
|
||||
|
|
@ -41,7 +47,7 @@ NETLIST_START(main)
|
|||
NET_C(RL.2, GND)
|
||||
NET_C(RL.1, op1.OUT)
|
||||
|
||||
LOG(logX, op1.OUT)
|
||||
//LOG(logX, op1.OUT)
|
||||
//LOG(logY, clk)
|
||||
NETLIST_END()
|
||||
|
||||
|
|
@ -62,6 +68,8 @@ NETLIST_START(opamp)
|
|||
ALIAS(OUT, EBUF.OP) // Opamp output ...
|
||||
|
||||
ALIAS(GND, EBUF.ON) // GND terminal
|
||||
ALIAS(VCC, DUMMY.I) // VCC terminal
|
||||
DUMMY_INPUT(DUMMY)
|
||||
|
||||
/* The opamp model */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue