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ssimon speed switch
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parent
af0394e428
commit
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3 changed files with 30 additions and 4 deletions
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@ -1051,7 +1051,7 @@ void hh_tms1k_state::ebball3_set_clock()
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// MCU clock is from an RC circuit(R=47K, C=33pf) oscillating by default at ~340kHz,
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// MCU clock is from an RC circuit(R=47K, C=33pf) oscillating by default at ~340kHz,
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// but on PRO, the difficulty switch adds an extra 150K resistor to Vdd to speed
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// but on PRO, the difficulty switch adds an extra 150K resistor to Vdd to speed
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// it up to around ~440kHz.
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// it up to around ~440kHz.
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m_maincpu->set_unscaled_clock(m_inp_matrix[3]->read() & 1 ? 440000 : 340000);
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m_maincpu->set_unscaled_clock((m_inp_matrix[3]->read() & 1) ? 440000 : 340000);
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}
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}
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INPUT_CHANGED_MEMBER(hh_tms1k_state::ebball3_difficulty_switch)
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INPUT_CHANGED_MEMBER(hh_tms1k_state::ebball3_difficulty_switch)
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@ -1570,17 +1570,38 @@ static INPUT_PORTS_START( ssimon )
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PORT_BIT( 0x0d, IP_ACTIVE_HIGH, IPT_UNUSED )
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PORT_BIT( 0x0d, IP_ACTIVE_HIGH, IPT_UNUSED )
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PORT_START("IN.6") // fake
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PORT_START("IN.6") // fake
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PORT_CONFNAME( 0x03, 0x00, "Speed" ) //PORT_CHANGED_MEMBER(DEVICE_SELF, hh_tms1k_state, ssimon_speed_switch, NULL)
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PORT_CONFNAME( 0x03, 0x01, "Speed" ) PORT_CHANGED_MEMBER(DEVICE_SELF, hh_tms1k_state, ssimon_speed_switch, NULL)
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PORT_CONFSETTING( 0x00, "Simple" )
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PORT_CONFSETTING( 0x00, "Simple" )
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PORT_CONFSETTING( 0x01, "Normal" )
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PORT_CONFSETTING( 0x01, "Normal" )
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PORT_CONFSETTING( 0x02, "Super" )
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PORT_CONFSETTING( 0x02, "Super" )
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INPUT_PORTS_END
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INPUT_PORTS_END
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void hh_tms1k_state::ssimon_set_clock()
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{
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// MCU clock is from an RC circuit with C=100pf, R=x depending on speed switch:
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// 0 Simple: R=51K -> ~200kHz
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// 1 Normal: R=37K -> ~275kHz
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// 2 Super: R=22K -> ~400kHz
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UINT8 inp = m_inp_matrix[6]->read();
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m_maincpu->set_unscaled_clock((inp & 2) ? 400000 : ((inp & 1) ? 275000 : 200000));
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}
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INPUT_CHANGED_MEMBER(hh_tms1k_state::ssimon_speed_switch)
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{
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ssimon_set_clock();
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}
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MACHINE_RESET_MEMBER(hh_tms1k_state, ssimon)
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{
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machine_reset();
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ssimon_set_clock();
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}
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static MACHINE_CONFIG_START( ssimon, hh_tms1k_state )
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static MACHINE_CONFIG_START( ssimon, hh_tms1k_state )
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/* basic machine hardware */
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", TMS1100, 350000) // x
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MCFG_CPU_ADD("maincpu", TMS1100, 275000) // see ssimon_set_clock
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MCFG_TMS1XXX_READ_K_CB(READ8(hh_tms1k_state, ssimon_read_k))
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MCFG_TMS1XXX_READ_K_CB(READ8(hh_tms1k_state, ssimon_read_k))
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MCFG_TMS1XXX_WRITE_R_CB(WRITE16(hh_tms1k_state, ssimon_write_r))
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MCFG_TMS1XXX_WRITE_R_CB(WRITE16(hh_tms1k_state, ssimon_write_r))
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MCFG_TMS1XXX_WRITE_O_CB(WRITE16(hh_tms1k_state, ssimon_write_o))
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MCFG_TMS1XXX_WRITE_O_CB(WRITE16(hh_tms1k_state, ssimon_write_o))
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@ -1588,6 +1609,8 @@ static MACHINE_CONFIG_START( ssimon, hh_tms1k_state )
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MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_tms1k_state, display_decay_tick, attotime::from_msec(1))
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MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_tms1k_state, display_decay_tick, attotime::from_msec(1))
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MCFG_DEFAULT_LAYOUT(layout_ssimon)
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MCFG_DEFAULT_LAYOUT(layout_ssimon)
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MCFG_MACHINE_RESET_OVERRIDE(hh_tms1k_state, ssimon)
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/* no video! */
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/* no video! */
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/* sound hardware */
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/* sound hardware */
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@ -770,7 +770,7 @@ void hh_ucom4_state::tmtennis_set_clock()
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// MCU clock is from an LC circuit oscillating by default at ~360kHz,
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// MCU clock is from an LC circuit oscillating by default at ~360kHz,
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// but on PRO1, the difficulty switch puts a capacitor across the LC circuit
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// but on PRO1, the difficulty switch puts a capacitor across the LC circuit
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// to slow it down to ~260kHz.
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// to slow it down to ~260kHz.
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m_maincpu->set_unscaled_clock(m_inp_matrix[1]->read() & 0x100 ? 260000 : 360000);
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m_maincpu->set_unscaled_clock((m_inp_matrix[1]->read() & 0x100) ? 260000 : 360000);
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}
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}
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INPUT_CHANGED_MEMBER(hh_ucom4_state::tmtennis_difficulty_switch)
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INPUT_CHANGED_MEMBER(hh_ucom4_state::tmtennis_difficulty_switch)
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@ -112,6 +112,9 @@ public:
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DECLARE_WRITE16_MEMBER(ssimon_write_r);
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DECLARE_WRITE16_MEMBER(ssimon_write_r);
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DECLARE_WRITE16_MEMBER(ssimon_write_o);
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DECLARE_WRITE16_MEMBER(ssimon_write_o);
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DECLARE_READ8_MEMBER(ssimon_read_k);
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DECLARE_READ8_MEMBER(ssimon_read_k);
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void ssimon_set_clock();
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DECLARE_INPUT_CHANGED_MEMBER(ssimon_speed_switch);
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DECLARE_MACHINE_RESET(ssimon);
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DECLARE_WRITE16_MEMBER(cnsector_write_r);
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DECLARE_WRITE16_MEMBER(cnsector_write_r);
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DECLARE_WRITE16_MEMBER(cnsector_write_o);
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DECLARE_WRITE16_MEMBER(cnsector_write_o);
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