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Added 9602 one-shot to netlist. (nw)
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commit
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4 changed files with 148 additions and 17 deletions
51
nl_examples/9602_mstable.c
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51
nl_examples/9602_mstable.c
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@ -0,0 +1,51 @@
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/*
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* 9602_mstable.c
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*
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*/
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#include "netlist/devices/net_lib.h"
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NETLIST_START(74123_mstable)
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/*
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* Monoflog
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*
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*/
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/* Standard stuff */
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SOLVER(Solver, 48000)
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ANALOG_INPUT(V5, 5) // 5V
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/* Wiring up the 74123 */
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CLOCK(clk, 50)
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TTL_9602_DIP(mf)
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RES(R, 10000)
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CAP(C, 1e-6)
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NET_C(GND, mf.8) //
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NET_C(V5, mf.16) //
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NET_C(C.1, mf.1)
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NET_C(mf.1, GND) // Test - can be removed
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NET_C(C.2, mf.2, R.2)
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NET_C(R.1, V5)
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NET_C(mf.3, V5) // CLR
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NET_C(mf.4, GND) // B
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NET_C(mf.5, clk.Q) // A
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LOG(logC, C.2)
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LOG(logQ, mf.6) //Q
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LOG(logX, clk.Q)
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// avoid non connected inputs
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NET_C(mf.11, V5)
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NET_C(mf.12, V5)
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NET_C(mf.13, V5)
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NETLIST_END()
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@ -144,6 +144,7 @@ void nl_initialize_factory(netlist_factory_t &factory)
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ENTRY(74107_dip, TTL_74107_DIP, "-")
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ENTRY(74123_dip, TTL_74123_DIP, "-")
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ENTRY(74153_dip, TTL_74153_DIP, "-")
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ENTRY(9602_dip, TTL_9602_DIP, "-")
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ENTRY(9316_dip, TTL_9316_DIP, "-")
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ENTRY(SN74LS629_dip, SN74LS629_DIP, "1.CAP1,2.CAP2")
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ENTRY(NE555_dip, NE555_DIP, "-")
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@ -10,6 +10,8 @@
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NETLIB_START(74123)
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{
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m_dev_type = 74123;
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register_sub(m_RP, "RP");
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register_sub(m_RN, "RN");
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@ -41,7 +43,13 @@ NETLIB_START(74123)
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NETLIB_UPDATE(74123)
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{
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const netlist_sig_t m_trig = (INPLOGIC(m_A) ^ 1) & INPLOGIC(m_B) & INPLOGIC(m_CLRQ);
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netlist_sig_t m_trig;
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if (m_dev_type == 74123)
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m_trig = (INPLOGIC(m_A) ^ 1) & INPLOGIC(m_B) & INPLOGIC(m_CLRQ);
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else
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// 9602
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m_trig = (INPLOGIC(m_A) ^ 1) | INPLOGIC(m_B);
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if (!INPLOGIC(m_CLRQ))
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{
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@ -104,26 +112,28 @@ NETLIB_RESET(74123)
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NETLIB_START(74123_dip)
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{
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#if 0
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register_sub(m_1, "1");
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register_sub(m_2, "2");
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register_sub(m_3, "3");
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register_subalias("1", m_1.m_i[0]);
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register_subalias("2", m_1.m_i[1]);
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register_subalias("3", m_2.m_i[0]);
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register_subalias("4", m_2.m_i[1]);
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register_subalias("5", m_2.m_i[2]);
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register_subalias("6", m_2.m_Q);
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register_subalias("1", m_1.m_A);
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register_subalias("2", m_1.m_B);
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register_subalias("3", m_1.m_CLRQ);
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register_subalias("4", m_1.m_QQ);
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register_subalias("5", m_2.m_Q);
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register_subalias("6", m_2.m_RN.m_N);
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register_subalias("7", m_2.m_RN.m_P);
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register_subalias("8", m_1.m_RN.m_N);
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connect(m_1.m_RN.m_N, m_2.m_RN.m_N);
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register_subalias("8", m_3.m_Q);
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register_subalias("9", m_3.m_i[0]);
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register_subalias("10", m_3.m_i[1]);
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register_subalias("11", m_3.m_i[2]);
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register_subalias("12", m_1.m_Q);
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register_subalias("13", m_1.m_i[2]);
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#endif
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register_subalias("9", m_2.m_A);
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register_subalias("10", m_2.m_B);
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register_subalias("11", m_2.m_CLRQ);
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register_subalias("12", m_2.m_QQ);
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register_subalias("13", m_1.m_Q);
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register_subalias("14", m_1.m_RN.m_N);
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register_subalias("15", m_1.m_RN.m_P);
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register_subalias("16", m_1.m_RP.m_P);
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connect(m_1.m_RP.m_P, m_2.m_RP.m_P);
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}
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NETLIB_UPDATE(74123_dip)
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@ -138,3 +148,45 @@ NETLIB_RESET(74123_dip)
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m_1.do_reset();
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m_2.do_reset();
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}
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NETLIB_START(9602_dip)
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{
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register_sub(m_1, "1");
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register_sub(m_2, "2");
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m_1.m_dev_type = 9602;
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m_2.m_dev_type = 9602;
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register_subalias("1", m_1.m_RN.m_N); // C1
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register_subalias("2", m_1.m_RN.m_P); // RC1
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register_subalias("3", m_1.m_CLRQ);
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register_subalias("4", m_1.m_B);
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register_subalias("5", m_1.m_A);
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register_subalias("6", m_1.m_Q);
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register_subalias("7", m_1.m_QQ);
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register_subalias("8", m_1.m_RN.m_N);
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connect(m_1.m_RN.m_N, m_2.m_RN.m_N);
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register_subalias("9", m_2.m_QQ);
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register_subalias("10", m_2.m_Q);
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register_subalias("11", m_2.m_A);
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register_subalias("12", m_2.m_B);
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register_subalias("13", m_2.m_CLRQ);
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register_subalias("14", m_2.m_RN.m_P); // RC2
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register_subalias("15", m_2.m_RN.m_N); // C2
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register_subalias("16", m_1.m_RP.m_P);
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connect(m_1.m_RP.m_P, m_2.m_RP.m_P);
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}
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NETLIB_UPDATE(9602_dip)
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{
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/* only called during startup */
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m_1.update_dev();
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m_2.update_dev();
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}
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NETLIB_RESET(9602_dip)
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{
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m_1.do_reset();
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m_2.do_reset();
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}
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@ -18,6 +18,18 @@
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*
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* Naming conventions follow Fairchild Semiconductor datasheet
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*
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* DM9602: Dual Retriggerable, Resettable One Shots
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*
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* +--------------+
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* C1 |1 ++ 16| VCC
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* RC1 |2 15| C2
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* CLR1 |3 14| RC2
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* B1 |4 9602 13| CLR2
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* A1 |5 12| B2
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* Q1 |6 11| A2
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* Q1Q |7 10| Q2
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* GND |8 9| Q2Q
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* +--------------+
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*/
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#ifndef NLD_74123_H_
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netlist_param_double_t m_K;
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netlist_param_double_t m_RI;
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int m_dev_type;
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);
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#define TTL_74123_DIP(_name) \
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);
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/* The 9602 is very similar to the 123. Input triggering is slightly different
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* THe 9602 uses an OR gate instead of an AND gate.
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*/
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#define TTL_9602_DIP(_name) \
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NET_REGISTER_DEV(9602_dip, _name)
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NETLIB_DEVICE(9602_dip,
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NETLIB_NAME(74123) m_1;
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NETLIB_NAME(74123) m_2;
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);
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#endif /* NLD_74123_H_ */
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