mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-28 09:58:33 +01:00
121 lines
3.8 KiB
Verilog
121 lines
3.8 KiB
Verilog
//--------------------------------------------------------------------------------------------------
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//
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// instruction decoder
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//
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//--------------------------------------------------------------------------------------------------
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`include "decstates.v"
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/*
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* order of register in 4 op blocs has several common combinations
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*/
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wire [3:0] reg_ABCD;
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wire [3:0] reg_BCAC;
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wire [3:0] reg_ABAC;
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wire [3:0] reg_BCCD;
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wire [3:0] reg_D0D1;
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assign reg_ABCD = {2'b00, nb_in[1:0]};
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assign reg_BCAC = {2'b00, nb_in[0], !(nb_in[1] || nb_in[0])};
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assign reg_ABAC = {2'b00, nb_in[1] && nb_in[0], (!nb_in[1]) && nb_in[0]};
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assign reg_BCCD = {2'b00, nb_in[1] || nb_in[0], (!nb_in[1]) ^ nb_in[0]};
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assign reg_D0D1 = {3'b010, (nb_in[0] && nb_in[1]) || (nb_in[2] && nb_in[3])};
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always @(posedge dec_strobe) begin
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if (alu_requested_halt) decode_error <= 1;
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if ((next_cycle == `BUSCMD_LOAD_PC)|
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(next_cycle == `BUSCMD_CONFIGURE)|
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(next_cycle == `BUSCMD_RESET)|
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((next_cycle == `BUSCMD_NOP)&
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(decstate == `DEC_START))) begin
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$display("SETTING next_cycle to BUSCMD_PC_READ");
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next_cycle <= `BUSCMD_PC_READ;
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end else begin
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`ifdef SIM
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if ((decstate == `DEC_START)|(decstate == `DEC_TEST_GO)) begin
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// display registers
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$display("PC: %05h Carry: %b h: %s rp: %h RSTK7: %05h", PC, Carry, hex_dec?"DEC":"HEX", rstk_ptr, RSTK[7]);
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$display("P: %h HST: %b ST: %b RSTK6: %5h", P, HST, ST, RSTK[6]);
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$display("A: %h R0: %h RSTK5: %5h", A, R0, RSTK[5]);
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$display("B: %h R1: %h RSTK4: %5h", B, R1, RSTK[4]);
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$display("C: %h R2: %h RSTK3: %5h", C, R2, RSTK[3]);
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$display("D: %h R3: %h RSTK2: %5h", D, R3, RSTK[2]);
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$display("D0: %h D1: %h R4: %h RSTK1: %5h", D0, D1, R4, RSTK[1]);
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$display(" RSTK0: %5h", RSTK[0]);
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end
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`endif
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$display("CYCLE %d | NEXTC %h | INSTR %d | PC %h | DECSTATE %3h | NIBBLE %h",
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cycle_ctr, next_cycle,
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(decstate == `DEC_START)?instr_ctr+1:instr_ctr,
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PC, decstate, nb_in);
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case (decstate)
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`DEC_START: begin
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// disable ALU debugging at the start of a new instruction
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alu_debug <= 0;
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// reset debugger op_code
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dbg_op_code <= 0;
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instr_ctr <= instr_ctr + 1;
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inst_start_PC <= PC;
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case (nb_in)
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4'h0: decstate <= `DEC_0X;
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4'h1: decstate <= `DEC_1X;
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4'h2: decstate <= `DEC_P_EQ_N;
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4'h3: decstate <= `DEC_LC;
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4'h6: decstate <= `DEC_GOTO;
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4'h7: decstate <= `DEC_GOSUB;
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4'h8: decstate <= `DEC_8X;
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4'hA: begin
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fields_return <= `DEC_Axx_EXEC;
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decstate <= `DEC_ab_FIELDS;
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end
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4'hB: begin
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fields_return <= `DEC_Bxx_EXEC;
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decstate <= `DEC_ab_FIELDS;
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end
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4'hC: decstate <= `DEC_CX;
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4'hD: decstate <= `DEC_DX;
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4'hF: decstate <= `DEC_FX;
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default: begin
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$display("ERROR : DEC_START");
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decode_error <= 1;
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end
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endcase
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end
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`include "opcodes/0x.v"
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`include "opcodes/1x.v"
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`include "opcodes/13x_ptr_and_AC.v"
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`include "opcodes/1[45]_memaccess.v"
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`include "opcodes/1[678C]n_D[01]_math_n.v"
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`include "opcodes/1[9ABDEF]nnnnn_D[01]_EQ_[245]n.v"
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`include "opcodes/2n_P_EQ_n.v"
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`include "opcodes/3n[x...]_LC.v"
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`include "opcodes/6xxx_GOTO.v"
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`include "opcodes/7xxx_GOSUB.v"
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`include "opcodes/8x.v"
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`include "opcodes/80x.v"
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`include "opcodes/808x.v"
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`include "opcodes/808[4-B]_[AC]BIT_set_test.v"
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`include "opcodes/80[CD]n_C_and_P_n.v"
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`include "opcodes/82x_CLRHST.v"
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`include "opcodes/8[4567]n_work_test_ST.v"
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`include "opcodes/8[89]n_test_P.v"
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`include "opcodes/8Ax_test_[n]eq_A.v"
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`include "opcodes/8[DF]xxxxx_GO.v"
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`include "opcodes/A[ab]x.v"
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`include "opcodes/B[ab]x.v"
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`include "opcodes/Cx.v"
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`include "opcodes/Dx_regs_field_A.v"
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`include "opcodes/Fx.v"
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`include "opcodes/xx_RTNYES_GOYES.v"
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`include "opcodes/z_alu_phase_3.v"
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`include "opcodes/z_fields.v"
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default: begin
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$display("ERROR : GENERAL");
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decode_error <= 1;
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end
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endcase
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end
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end
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