mirror of
https://github.com/sxpert/hp-saturn
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54 lines
No EOL
1.3 KiB
Verilog
54 lines
No EOL
1.3 KiB
Verilog
/*
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* Alu module
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* calculations are in here
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*/
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`include "fields.v"
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`DEC_ALU_INIT, `DEC_ALU_CONT: begin
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`ifdef SIM
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if (alu_debug) begin
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$display("------------------------------- z_alu_phase_3 ---------------------------------");
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$display("alu_src1 %h | alu_src2 %h | alu_tmp %h | alu_carry %b",
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alu_src1, alu_src2, alu_tmp, alu_carry);
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end
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`endif
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case (alu_op)
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`ALU_OP_ZERO: begin
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$display("ALU_OP_ZERO");
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case (alu_reg_dest)
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`ALU_REG_A: A[alu_first*4+:4] <= 0;
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`ALU_REG_B: B[alu_first*4+:4] <= 0;
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`ALU_REG_C: C[alu_first*4+:4] <= 0;
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`ALU_REG_D: D[alu_first*4+:4] <= 0;
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default: $display("ALU_OP_ZERO register not handled");
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endcase
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alu_first <= (alu_first + 1) & 4'hF;
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end
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`ALU_OP_SHR: begin
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end
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`ALU_OP_INC: begin
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$display("ALU_OP_INC");
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case (alu_reg_dest)
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`ALU_REG_D: {Carry, D[alu_first*4+:4]} <= alu_src1 + alu_carry;
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default: $display("ALU_OP_INC register not handled");
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endcase
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alu_first <= (alu_first + 1) & 4'hF;
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end
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default: begin
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`ifdef SIM
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`endif
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end
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endcase
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if (alu_last == alu_first) begin
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// the alu is done
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decstate <= `DEC_START;
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alu_requested_halt <= alu_halt;
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end else decstate <= `DEC_ALU_CONT;
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end |