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https://github.com/sxpert/hp-saturn
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18 lines
No EOL
506 B
Verilog
18 lines
No EOL
506 B
Verilog
/******************************************************************************
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*1[678C] D[01]=D[01][+-] (n+1)
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*
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*
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*/
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`DEC_PTR_MATH: begin
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case ({t_ptr, t_add_sub})
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2'b00: {Carry, D0} <= D0 + (nb_in + 1);
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2'b01: {Carry, D0} <= D0 - (nb_in + 1);
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2'b10: {Carry, D1} <= D1 + (nb_in + 1);
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2'b11: {Carry, D1} <= D1 - (nb_in + 1);
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endcase
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%5h D%b=D%b%s\t%2d", inst_start_PC, t_ptr, t_ptr, t_add_sub?"-":"+", nb_in+1);
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`endif
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end |