mirror of
https://github.com/sxpert/hp-saturn
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cbfbe4eb3f
add add_cst and sub_cst alu opcodes port pointer math to use ALU make A[ab]x more readable
32 lines
836 B
Verilog
32 lines
836 B
Verilog
/******************************************************************************
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* 1X
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*
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*
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*/
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`include "decstates.v"
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`DEC_1X: begin
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case (nb_in)
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4'h3: decstate <= `DEC_13X;
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4'h4: decstate <= `DEC_14X;
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4'h5: decstate <= `DEC_15X;
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4'h6, 4'h7, 4'h8, 4'hC: begin
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alu_reg_dest <= reg_D0D1;
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alu_reg_src1 <= reg_D0D1;
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alu_reg_src2 <= `ALU_REG_CST;
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alu_op <= nb_in[3]?`ALU_OP_SUB_CST:`ALU_OP_ADD_CST;
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decstate <= `DEC_PTR_MATH;
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end
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4'h9: decstate <= `DEC_D0_EQ_2N;
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4'hA: decstate <= `DEC_D0_EQ_4N;
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4'hB: decstate <= `DEC_D0_EQ_5N;
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4'hD: decstate <= `DEC_D1_EQ_2N;
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4'hE: decstate <= `DEC_D1_EQ_4N;
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4'hF: decstate <= `DEC_D1_EQ_5N;
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default: begin
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$display("ERROR : DEC_1X %h", nb_in);
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decode_error <= 1;
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end
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endcase
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end
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