mirror of
https://github.com/sxpert/hp-saturn
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61 lines
1.6 KiB
Verilog
61 lines
1.6 KiB
Verilog
/******************************************************************************
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* 8
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* a lot of things start with 8...
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*
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*/
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`include "decstates.v"
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`DEC_FX: begin
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case (nb_in)
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4'h8, 4'h9, 4'hA, 4'hB: begin
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if (!hex_dec) begin
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case (nb_in)
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4'h8: {Carry, A[19:0]} <= - A[19:0];
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4'h9: {Carry, B[19:0]} <= - B[19:0];
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4'hA: {Carry, C[19:0]} <= - C[19:0];
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4'hB: {Carry, D[19:0]} <= - D[19:0];
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endcase
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decstate <= `DEC_START;
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end
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`ifdef SIM
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$write("%5h ", inst_start_PC);
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case (nb_in)
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4'h8: $write("A=-A");
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4'h8: $write("B=-B");
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4'h8: $write("C=-C");
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4'h8: $write("D=-D");
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endcase
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if (!hex_dec) $display("\tA");
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else $display("\tA\t\t\t <=== DEC MODE NOT IMPLEMENTED");
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`endif
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end
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4'hC, 4'hD, 4'hE, 4'hF: begin
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if (!hex_dec) begin
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case (nb_in)
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4'hC: {Carry, A[19:0]} <= - A[19:0] - 1;
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4'hD: {Carry, B[19:0]} <= - B[19:0] - 1;
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4'hE: {Carry, C[19:0]} <= - C[19:0] - 1;
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4'hF: {Carry, D[19:0]} <= - D[19:0] - 1;
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endcase
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decstate <= `DEC_START;
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end
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`ifdef SIM
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$write("%5h ", inst_start_PC);
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case (nb_in)
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4'h8: $write("A=-A-1");
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4'h8: $write("B=-B-1");
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4'h8: $write("C=-C-1");
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4'h8: $write("D=-D-1");
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endcase
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if (!hex_dec) $display("\tA");
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else $display("\tA\t\t\t <=== DEC MODE NOT IMPLEMENTED");
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`endif
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end
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default: begin
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$display("ERROR : DEC_FX");
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decode_error <= 1;
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end
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endcase
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end
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