mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
151 lines
4.5 KiB
Verilog
151 lines
4.5 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`ifndef _SATURN_TEST_ROM
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`define _SATURN_TEST_ROM
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`include "def-buscmd.v"
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/******************************************************************************
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*
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* test rom
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*
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****************************************************************************/
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module saturn_test_rom (
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i_stalled,
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i_reset,
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i_bus_data_in,
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o_bus_data_out,
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i_bus_strobe,
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i_bus_cmd_data
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);
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input wire [0:0] i_stalled;
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input wire [0:0] i_reset;
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input wire [3:0] i_bus_data_in;
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output reg [3:0] o_bus_data_out;
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input wire [0:0] i_bus_strobe;
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input wire [0:0] i_bus_cmd_data;
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reg [31:0] cycles;
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`ifdef SIM
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`define ROMBITS 20
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`else
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`define ROMBITS 12
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`endif
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reg [3:0] rom [0:2**`ROMBITS-1];
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reg [19:0] local_pc;
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reg [19:0] local_dp;
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reg [3:0] last_bus_cmd;
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reg [2:0] addr_c;
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wire [0:0] s_load_pc;
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wire [0:0] s_load_dp;
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wire [0:0] s_pc_read;
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wire [0:0] s_dp_read;
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wire [0:0] s_dp_write;
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assign s_load_pc = (last_bus_cmd == `BUSCMD_LOAD_PC);
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assign s_load_dp = (last_bus_cmd == `BUSCMD_LOAD_DP);
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assign s_pc_read = (last_bus_cmd == `BUSCMD_PC_READ);
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assign s_dp_read = (last_bus_cmd == `BUSCMD_DP_READ);
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assign s_dp_write = (last_bus_cmd == `BUSCMD_DP_WRITE);
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initial begin
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$readmemh("rom-gx-r.hex", rom, 0, 2**`ROMBITS-1);
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// $readmemh("testrom-2.hex", rom, 0, 2**`ROMBITS-1);
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// $monitor("rst %b | strb %b | c/d %b | bus_i %h | bus_o %h | last %h | slpc %b | addr_c %0d | lpc %5h | ldp %5h",
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// i_reset, i_bus_strobe, i_bus_cmd_data, i_bus_data_in, o_bus_data_out,
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// last_bus_cmd, s_load_pc, addr_c, local_pc, local_dp);
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end
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always @(posedge i_bus_strobe) begin
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if (i_reset) begin
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cycles <= 0;
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last_bus_cmd <= `BUSCMD_NOP;
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addr_c <= 0;
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local_pc <= 0;
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local_dp <= 0;
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end
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if (!i_reset && !i_stalled)
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cycles <= cycles + 1;
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if (!i_stalled && !i_bus_cmd_data ) begin
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$write("ROM : [%d] COMMAND ", cycles);
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case (i_bus_data_in)
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`BUSCMD_PC_READ: $write("PC_READ"); // 2
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`BUSCMD_DP_WRITE: $write("DP_WRITE"); // 5
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`BUSCMD_LOAD_PC: $write("LOAD_PC"); // 6
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`BUSCMD_LOAD_DP: $write("LOAD_DP"); // 7
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`BUSCMD_CONFIGURE: $write("CONFIGURE (ignore)"); // 8
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`BUSCMD_RESET: $write("RESET (ignore)"); // 15
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endcase
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$write(" (%h)\n", i_bus_data_in);
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last_bus_cmd <= i_bus_data_in;
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end
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if (!i_stalled && i_bus_cmd_data && s_load_pc) begin
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$display("ROM : [%d] ADDR_IN(%0d) %h => PC [%5h]", cycles, addr_c, i_bus_data_in, local_pc);
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local_pc[addr_c*4+:4] <= i_bus_data_in;
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if (addr_c == 4) $display("ROM : [%d] auto PC_READ [%5h]", cycles, {i_bus_data_in, local_pc[15:0]});
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last_bus_cmd <= (addr_c == 4)?`BUSCMD_PC_READ:last_bus_cmd;
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addr_c <= (addr_c == 4)?0:addr_c + 1;
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end
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if (!i_stalled && i_bus_cmd_data && s_load_dp) begin
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$display("ROM : [%d] ADDR_IN(%0d) %h => DP [%5h]", cycles, addr_c, i_bus_data_in, local_dp);
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local_dp[addr_c*4+:4] <= i_bus_data_in;
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if (addr_c == 4) $display("ROM : [%d] auto DP_READ [%5h]", cycles, {i_bus_data_in, local_dp[15:0]});
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last_bus_cmd <= (addr_c == 4)?`BUSCMD_DP_READ:last_bus_cmd;
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addr_c <= (addr_c == 4)?0:addr_c + 1;
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end
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if (!i_stalled && i_bus_cmd_data && s_pc_read) begin
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o_bus_data_out <= rom[local_pc[`ROMBITS-1:0]];
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$display("ROM : [%d] %h <= PC_READ [%5h]", cycles, rom[local_pc[`ROMBITS-1:0]], local_pc);
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local_pc <= local_pc + 1;
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end
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if (!i_stalled && i_bus_cmd_data && s_dp_read) begin
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o_bus_data_out <= rom[local_dp[`ROMBITS-1:0]];
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$display("ROM : [%d] %h <= DP_READ [%5h]", cycles, rom[local_dp[`ROMBITS-1:0]], local_dp);
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local_dp <= local_dp + 1;
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end
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if (!i_stalled && i_bus_cmd_data && s_dp_write) begin
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$display("ROM : [%d] %h => DP_WRITE [%5h] (ignored)", cycles, i_bus_data_in, local_dp);
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local_dp <= local_dp + 1;
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end
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end
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endmodule
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`endif
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