mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
339 lines
8.9 KiB
Verilog
339 lines
8.9 KiB
Verilog
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/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`ifndef _SATURN_ALU_PC
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`define _SATURN_ALU_PC
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`default_nettype none //
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module saturn_alu_pc (
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i_clk,
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i_reset,
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i_stalled,
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i_just_reset,
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i_alu_active,
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i_cycle_ctr,
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i_phase,
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i_phase_0,
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i_phase_2,
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i_phase_3,
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i_alu_initializing,
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i_v_dest_counter_ptr,
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o_bus_address,
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o_bus_load_pc,
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i_bus_nibble_in,
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i_alu_stall_dec,
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i_ins_rtn,
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i_ins_test_go,
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i_push,
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i_pop,
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i_mode_jmp,
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i_carry,
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i_op_jump,
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i_op_jmp_rel_2,
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i_op_jmp_rel_3,
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i_op_jmp_rel_4,
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i_op_jmp_abs_5,
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o_do_apply_jump,
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`ifdef SIM
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o_pc,
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o_rstk_ptr,
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o_rstk_0,
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o_rstk_1,
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o_rstk_2,
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o_rstk_3,
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o_rstk_4,
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o_rstk_5,
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o_rstk_6,
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o_rstk_7
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`else
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o_pc
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`endif
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [0:0] i_stalled;
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input wire [0:0] i_just_reset;
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input wire [0:0] i_alu_active;
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input wire [31:0] i_cycle_ctr;
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input wire [1:0] i_phase;
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input wire [0:0] i_phase_0;
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input wire [0:0] i_phase_2;
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input wire [0:0] i_phase_3;
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input wire [0:0] i_alu_initializing;
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input wire [2:0] i_v_dest_counter_ptr;
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output reg [19:0] o_bus_address;
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output reg [0:0] o_bus_load_pc;
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input wire [3:0] i_bus_nibble_in;
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input wire [0:0] i_alu_stall_dec;
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input wire [0:0] i_ins_rtn;
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input wire [0:0] i_ins_test_go;
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input wire [0:0] i_push;
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input wire [0:0] i_pop;
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input wire [0:0] i_mode_jmp;
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input wire [0:0] i_carry;
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input wire [0:0] i_op_jump;
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input wire [0:0] i_op_jmp_rel_2;
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input wire [0:0] i_op_jmp_rel_3;
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input wire [0:0] i_op_jmp_rel_4;
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input wire [0:0] i_op_jmp_abs_5;
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output wire [0:0] o_do_apply_jump;
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output wire [19:0] o_pc;
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`ifdef SIM
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output wire [2:0] o_rstk_ptr;
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output wire [19:0] o_rstk_0;
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output wire [19:0] o_rstk_1;
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output wire [19:0] o_rstk_2;
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output wire [19:0] o_rstk_3;
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output wire [19:0] o_rstk_4;
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output wire [19:0] o_rstk_5;
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output wire [19:0] o_rstk_6;
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output wire [19:0] o_rstk_7;
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`endif
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/* module 5:
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* manages all that is linked with the program counter
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*/
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/* main PC and RSTK registers */
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reg [2:0] rstk_ptr;
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reg [19:0] PC;
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reg [19:0] RSTK[0:7];
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assign o_pc = PC;
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`ifdef SIM
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assign o_rstk_ptr = rstk_ptr;
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assign o_rstk_0 = RSTK[0];
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assign o_rstk_1 = RSTK[1];
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assign o_rstk_2 = RSTK[2];
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assign o_rstk_3 = RSTK[3];
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assign o_rstk_4 = RSTK[4];
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assign o_rstk_5 = RSTK[5];
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assign o_rstk_6 = RSTK[6];
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assign o_rstk_7 = RSTK[7];
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`endif
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// assign goyes_off = {{12{i_imm_value[3]}}, i_imm_value, jump_off[3:0]};
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// assign goyes_pc = jump_bse + goyes_off;
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// // rtnyes is already handled by i_ins_test_go
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// assign is_rtn_rel2 = (alu_op == `ALU_OP_JMP_REL2) && (goyes_off == 0);
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// assign is_jmp_rel2 = (alu_op == `ALU_OP_JMP_REL2) && !(goyes_off == 0);
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// assign jmp_carry_test = (i_test_carry && (CARRY == i_carry_val));
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// assign exec_rtn_rel2 = is_rtn_rel2 && jmp_carry_test && alu_done;
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// // assign set_jmp_rel2 = is_jmp_rel2 && jmp_carry_test && alu_finish;
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// assign exec_jmp_rel2 = is_jmp_rel2 && jmp_carry_test && alu_done;
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/* jump values generator */
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reg [2:0] jump_offset_counter;
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reg [19:0] jump_base;
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reg [15:0] jump_offset;
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reg [19:0] new_jump_offset;
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reg [0:0] jump_start;
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reg [0:0] jump_done;
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wire [0:0] jump_relative;
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assign jump_relative = i_op_jmp_rel_2 || i_op_jmp_rel_3 || i_op_jmp_rel_4;
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// wire [0:0] do_set_jump_base;
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wire [0:0] do_pre_calc_jump;
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wire [0:0] do_calc_jump;
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// assign do_set_jump_base = start_in_jmp_mode && !jump_done && jump_start;
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assign do_pre_calc_jump = !i_stalled && i_op_jump && i_phase_2 && !jump_done;
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assign do_calc_jump = i_mode_jmp && i_phase_3 && !jump_done;
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assign o_do_apply_jump = i_mode_jmp && i_phase_3 && jump_done;
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wire [19:0] jump_pc;
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assign jump_pc = jump_relative?(jump_base+new_jump_offset):new_jump_offset;
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/* pc update generator */
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reg [19:0] pc_plus_1;
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reg [2:0] rstk_ptr_plus_1;
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reg [2:0] rstk_ptr_minus_1;
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wire [19:0] next_pc;
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wire [0:0] update_pc;
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wire [0:0] reload_pc;
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wire [0:0] pop_pc;
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wire [0:0] push_pc;
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wire [0:0] pc_lines_cleanup;
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assign next_pc = (jump_done)?jump_pc:pc_plus_1;
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assign update_pc = (!i_reset && i_just_reset) || i_alu_active && i_phase_3 && (!i_alu_stall_dec) /* || exec_unc_jmp || exec_jmp_rel2 */;
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assign pop_pc = i_alu_active && i_phase_3 && i_pop && i_ins_rtn && ((!i_ins_test_go) || (i_ins_test_go && i_carry));
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assign push_pc = i_alu_active && i_push && o_do_apply_jump;
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assign reload_pc = (!i_reset && i_just_reset) || o_do_apply_jump || pop_pc;
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assign pc_lines_cleanup = i_alu_active && i_phase_0;
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always @(posedge i_clk) begin
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/*
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* initializes default values
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*/
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if (i_reset) begin
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PC <= ~0;
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o_bus_load_pc <= 0;
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rstk_ptr <= 0;
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jump_offset_counter <= 0;
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jump_base <= 0;
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jump_offset <= 0;
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jump_done <= 0;
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end
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/* on every clock, we update
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* pc + 1
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* rstk_ptr - 1
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* rstk_ptr + 1
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*/
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pc_plus_1 <= PC + 20'd1;
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rstk_ptr_minus_1 <= rstk_ptr - 3'd1;
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rstk_ptr_plus_1 <= rstk_ptr + 3'd1;
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/*
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* Similarly to the data registers,
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* initializes the RSTK while the PC is first loaded
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*
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*/
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if (i_alu_initializing)
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RSTK[i_v_dest_counter_ptr] <= 0;
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/**
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* handles jumps
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*
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*/
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/* nibble was read in phase 1
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* in phase 2, we precalculate all values for a jump
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*/
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if (do_pre_calc_jump) begin
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$display("ALU_PC %0d: [%d] pre_calc_jump %0d %h", i_phase, i_cycle_ctr, jump_offset_counter, i_bus_nibble_in);
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case (jump_offset_counter)
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0: begin
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new_jump_offset <= {{16{i_bus_nibble_in[3] && jump_relative}}, i_bus_nibble_in};
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jump_start <= 1'b1;
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jump_base <= PC;
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end
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1: begin
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new_jump_offset <= {{12{i_bus_nibble_in[3] && jump_relative}}, i_bus_nibble_in, jump_offset[ 3:0]};
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if (i_op_jmp_rel_2) jump_done <= 1'b1;
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end
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2: begin
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new_jump_offset <= {{ 8{i_bus_nibble_in[3] && jump_relative}}, i_bus_nibble_in, jump_offset[ 7:0]};
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if (i_op_jmp_rel_3) jump_done <= 1'b1;
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end
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3: begin
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new_jump_offset <= {{ 4{i_bus_nibble_in[3] && jump_relative}}, i_bus_nibble_in, jump_offset[11:0]};
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if (i_op_jmp_rel_4) jump_done <= 1'b1;
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end
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4: begin
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new_jump_offset <= {i_bus_nibble_in, jump_offset[15:0]};
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if (i_op_jmp_abs_5) jump_done <= 1'b1;
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end
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default: begin end
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endcase
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end
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/*
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* in phase 3, we either update the counter
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*/
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if (do_calc_jump) begin
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$display("ALU_PC %0d: [%d] calc jump %0d | nibble %h | rel %b | base %h | offset %h | jump_pc %h",
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i_phase, i_cycle_ctr, jump_offset_counter, i_bus_nibble_in, jump_relative, jump_base, new_jump_offset, jump_pc);
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jump_offset <= new_jump_offset[15:0];
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jump_offset_counter <= jump_offset_counter + 3'b1;
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end
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/*
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* or apply the jump
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*/
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if (o_do_apply_jump) begin
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$display("ALU_PC %0d: [%d] apply jump %0d | nibble %h | rel %b | base %h | offset %h | jump_pc %h",
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i_phase, i_cycle_ctr, jump_offset_counter, i_bus_nibble_in, jump_relative, jump_base, new_jump_offset, jump_pc);
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jump_offset_counter <= 3'b0;
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new_jump_offset <= 20'b0;
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jump_start <= 1'b0;
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jump_done <= 1'b0;
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end
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/**
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*
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* Update the PC.
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* Request the new PC be loaded to the other modules through
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* the bus if necessary
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*
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*/
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if (update_pc) begin
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// $display("ALU_PC %0d: [%d] update pc to %h", phase, i_cycle_ctr, next_pc);
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PC <= pop_pc ? RSTK[rstk_ptr_minus_1] : next_pc;
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end
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if (push_pc) begin
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$display("ALU_PC %0d: [%d] PUSH PC %5h to RSTK[%0d]", i_phase, i_cycle_ctr, pc_plus_1, rstk_ptr);
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RSTK[rstk_ptr] <= pc_plus_1;
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rstk_ptr <= rstk_ptr_plus_1;
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end
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// $display("pop %b && rtn %b && ((!go %b) || (go %b && c %b))",
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// i_pop, i_ins_rtn, !i_ins_test_go, i_ins_test_go, c_carry);
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if (pop_pc) begin
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$display("ALU_PC %0d: [%d] POP RSTK[%0d] to PC %5h", i_phase, i_cycle_ctr, rstk_ptr_minus_1, RSTK[rstk_ptr_minus_1]);
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rstk_ptr <= rstk_ptr_minus_1;
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RSTK[rstk_ptr_minus_1] <= 20'b0;
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end
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if (reload_pc) begin
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$display("ALU_PC %0d: [%d] $$$$ RELOADING PC to %h $$$$",
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i_phase, i_cycle_ctr, (pop_pc ? RSTK[rstk_ptr_minus_1] : next_pc));
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o_bus_address <= pop_pc ? RSTK[rstk_ptr_minus_1] : next_pc;
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o_bus_load_pc <= 1'b1;
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end
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if (pc_lines_cleanup && o_bus_load_pc)
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o_bus_load_pc <= 1'b0;
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end
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endmodule
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`endif
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