mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
85 lines
No EOL
2 KiB
Verilog
85 lines
No EOL
2 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`include "saturn_def_alu.v"
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module saturn_alu_module (
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i_clk,
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i_clk_en,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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i_opcode,
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i_ptr_begin,
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i_ptr_end,
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i_run,
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i_done,
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i_prep_src_1_val,
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i_prep_src_2_val,
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i_prep_carry,
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i_calc_pos,
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o_calc_res_1_val,
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o_calc_res_2_val,
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o_calc_carry,
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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input wire [4:0] i_opcode;
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input wire [3:0] i_ptr_begin;
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input wire [3:0] i_ptr_end;
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input wire [0:0] i_run;
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input wire [0:0] i_done;
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input wire [3:0] i_prep_src_1_val;
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input wire [3:0] i_prep_src_2_val;
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input wire [0:0] i_prep_carry;
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input wire [3:0] i_calc_pos;
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output reg [3:0] o_calc_res_1_val;
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output reg [3:0] o_calc_res_2_val;
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output reg [0:0] o_calc_carry;
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always @(*) begin
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o_calc_res_1_val = 4'h0;
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o_calc_res_2_val = 4'h0;
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o_calc_carry = 2'b0;
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if (i_clk_en && i_run && !i_done) begin
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case (i_opcode)
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`ALU_OP_ZERO: $display("ALU %0d: [%d] res1 <= 0", i_phase, i_cycle_ctr);
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default: $display("ALU %0d: [%d] invalid ALU opcode %0d", i_phase, i_cycle_ctr, i_opcode);
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endcase
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end
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end
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endmodule |