mirror of
https://github.com/sxpert/hp-saturn
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17 lines
299 B
Verilog
17 lines
299 B
Verilog
/******************************************************************************
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* 805 CONFIG
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*
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*
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*/
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`include "decstates.v"
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`include "bus_commands.v"
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begin
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next_cycle <= `BUSCMD_CONFIGURE;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h CONFIG", inst_start_PC);
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`endif
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end
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