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18 lines
335 B
Verilog
18 lines
335 B
Verilog
/******************************************************************************
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* 1X
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*
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*
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*/
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`include "decstates.v"
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`DEC_1X: begin
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case (nibble)
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4'h4: decstate <= `DEC_14X;
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4'hb: decstate <= `DEC_D0_EQ_5N;
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default: begin
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$display("ERROR : DEC_1X");
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decode_error <= 1;
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end
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endcase
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end
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