mirror of
https://github.com/sxpert/hp-saturn
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27 lines
No EOL
630 B
Verilog
27 lines
No EOL
630 B
Verilog
/******************************************************************************
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*1bnnnnn DO=(5) nnnnn
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*
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*
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*/
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`include "decstates.v"
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`DEC_D0_EQ_5N: begin
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t_cnt <= 4;
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t_ctr <= 1;
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D0[3:0] <= nibble;
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decstate <= `DEC_D0_EQ_5N_LOOP;
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end
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`DEC_D0_EQ_5N_LOOP: begin
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D0[t_ctr*4+:4] <= nibble;
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if (t_ctr == t_cnt) begin
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decstate <= `DEC_START;
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`ifdef SIM
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$write("%5h D0=(5)\t%1h", inst_start_PC, nibble);
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for(t_ctr = 0; t_ctr != t_cnt; t_ctr ++)
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$write("%1h", D0[(t_cnt - t_ctr - 4'h1)*4+:4]);
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$write("\n");
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`endif
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end else
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t_ctr <= t_ctr + 1;
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end |