mirror of
https://github.com/sxpert/hp-saturn
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51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
/******************************************************************************
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* 8Ax
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* a lot of things start with 8...
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*
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*/
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`include "decstates.v"
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`DEC_8AX: begin
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// prepare ALU for register A
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field <= `T_FIELD_A;
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alu_first <= 0;
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alu_last <= 4;
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alu_op <= nb_in[2]?`ALU_OP_TEST_NEQ:`ALU_OP_TEST_EQ;
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if (!nb_in[3]) begin
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alu_reg_src1 <= {2'b00, nb_in[0], !(nb_in[1] || nb_in[0])};
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alu_reg_src2 <= {2'b00, nb_in[1:0]};
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end
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else begin
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alu_reg_src1 <= {2'b00, nb_in[1:0]};
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alu_reg_src2 <= `ALU_REG_0;
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end
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// alu_debug <= 1;
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next_cycle <= `BUSCMD_NOP;
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decstate <= `DEC_ALU_INIT;
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alu_return <= `DEC_TEST_GO;
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`ifdef SIM
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$write("%5h ?", inst_start_PC);
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case ({2'b00, (nb_in[3]?nb_in[1:0]:{nb_in[0], !(nb_in[1] || nb_in[0])})})
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`ALU_REG_A: $write("A");
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`ALU_REG_B: $write("B");
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`ALU_REG_C: $write("C");
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`ALU_REG_D: $write("D");
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endcase
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$write("%s", nb_in[2]?"#":"=");
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case (nb_in[3]?`ALU_REG_0:{2'b00, nb_in[1:0]})
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`ALU_REG_A: $write("A");
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`ALU_REG_B: $write("B");
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`ALU_REG_C: $write("C");
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`ALU_REG_D: $write("D");
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`ALU_REG_0: $write("0");
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endcase
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$display("\tA");
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`endif
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end
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