mirror of
https://github.com/sxpert/hp-saturn
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23 lines
427 B
Verilog
23 lines
427 B
Verilog
/******************************************************************************
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* 80Cn C=P n
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*
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*
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*/
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`include "decstates.v"
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`DEC_C_EQ_P_N: begin
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C[nb_in*4+:4] <= P;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h C=P\t%h", inst_start_PC, nb_in);
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`endif
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end
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`DEC_P_EQ_C_N: begin
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P <= C[nb_in*4+:4];
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h P=C\t%h", inst_start_PC, nb_in);
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`endif
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end
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