mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-19 10:26:58 +01:00
97 lines
1.6 KiB
Verilog
97 lines
1.6 KiB
Verilog
`include "bus_commands.v"
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`ifndef _HP48_IO_RAM
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`define _HP48_IO_RAM
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/**************************************************************************************************
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*
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* I/O ram
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* length: 64 nibbles
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*
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*
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*/
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module hp48_io_ram (
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input strobe,
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input reset,
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input [19:0] address,
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input [3:0] command,
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input [3:0] nibble_in,
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output reg [3:0] nibble_out,
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output reg io_ram_active,
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output reg io_ram_error
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);
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localparam IO_RAM_LEN = 64;
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// localparam BUSCMD_DP_WRITE = C_BUSCMD_DP_WRITE;
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// localparam BUSCMD_CONFIGURE = C_BUSCMD_CONFIGURE;
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reg [0:0] configured;
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reg [19:0] base_addr;
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reg [19:0] pc_ptr;
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reg [19:0] data_ptr;
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reg [3:0] io_ram [0:IO_RAM_LEN-1];
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/*
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*
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*
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*/
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initial
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begin
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`ifdef SIM
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$display("io_ram: set unconfigured");
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`endif
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configured = 0;
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`ifdef SIM
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$display("io_ram: reset error flag");
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`endif
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io_ram_error = 1'b0;
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`ifdef SIM
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$display("io_ram: setting base address to 0");
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`endif
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base_addr = 0;
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`ifdef SIM
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$display("io_ram: setting data pointer to 0");
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`endif
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data_ptr = 0;
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`ifdef SIM
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$display("io_ram: initializing to 0");
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`endif
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for (base_addr = 0; base_addr < IO_RAM_LEN; base_addr++)
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begin
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`ifdef SIM
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$write(".");
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`endif
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io_ram[base_addr] <= 0;
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end
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`ifdef SIM
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$write("\n");
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$display("io_ram: initialized");
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`endif
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end
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/*
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*
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*
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*/
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always @(*)
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begin
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io_ram_active = 0;
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if ((command==`BUSCMD_PC_READ)|(command==`BUSCMD_DP_READ)|
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(command==`BUSCMD_PC_WRITE)|(command==`BUSCMD_PC_WRITE))
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io_ram_active = ((base_addr>=data_ptr)&(data_ptr<base_addr+IO_RAM_LEN))&(configured);
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end
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always @(posedge strobe)
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begin
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end
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endmodule
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`endif
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