mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
210 lines
6.4 KiB
Verilog
210 lines
6.4 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`include "saturn_def_buscmd.v"
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`ifdef SIM
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`define ROMBITS 20
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`else
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`define ROMBITS 19
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`endif
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module saturn_hp48gx_rom (
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i_clk,
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i_clk_en,
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i_reset,
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`ifdef SIM
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i_phase,
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i_cycle_ctr,
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`endif
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i_phase_0,
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i_debug_cycle,
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i_bus_clk_en,
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i_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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`ifdef SIM
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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`endif
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input wire [0:0] i_phase_0;
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input wire [0:0] i_debug_cycle;
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input wire [0:0] i_bus_clk_en;
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input wire [0:0] i_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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reg [3:0] rom_data[0:(2**`ROMBITS)-1];
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initial $readmemh("rom-gx-r.hex", rom_data, 0, (2**`ROMBITS)-1);
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reg [3:0] last_cmd;
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reg [2:0] addr_pos_ctr;
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reg [19:0] local_pc;
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reg [19:0] local_dp;
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reg [3:0] read_nibble;
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initial begin
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last_cmd = 4'b0;
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addr_pos_ctr = 3'b0;
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local_pc = 20'b0;
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local_dp = 20'b0;
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end
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/*
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* reading the rom
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*/
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wire [0:0] do_pc_read = (last_cmd == `BUSCMD_PC_READ);
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wire [0:0] do_dp_read = (last_cmd == `BUSCMD_DP_READ);
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wire [0:0] do_read = do_pc_read || do_dp_read;
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/* pre-read happens on phase 0 */
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wire [0:0] pre_read = i_clk_en && i_phase_0 && !i_debug_cycle && do_read;
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/* this happes on phase 1 */
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wire [0:0] can_read = i_bus_clk_en && i_bus_is_data && do_read;
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wire [19:0] access_pointer = do_pc_read?local_pc:local_dp;
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`ifndef SIM
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/* Verilator lint_off UNUSED */
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wire [19:`ROMBITS-1] access_pointer_unused = access_pointer[19:`ROMBITS-1];
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/* Verilator lint_on UNUSED */
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`endif
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wire [`ROMBITS-1:0] address = access_pointer[`ROMBITS-1:0];
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always @(posedge i_clk) begin
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if (pre_read) begin
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`ifdef SIM
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$display("ROM-GX-R %0d: [%d] pre_read %h <= rom[%5h]", i_phase, i_cycle_ctr, rom_data[address], address);
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`endif
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read_nibble <= rom_data[address];
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end
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end
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always @(posedge i_clk) begin
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if (can_read) begin
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`ifdef SIM
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$display("ROM-GX-R %0d: [%d] can_read %h <= rom[%5h]", i_phase, i_cycle_ctr, read_nibble, address);
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`endif
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o_bus_nibble_out <= read_nibble;
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end
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end
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`ifdef SIM
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wire [3:0] imm_nibble = rom_data[address];
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`endif
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/*
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* general case
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*/
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always @(posedge i_clk) begin
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if (i_bus_clk_en && i_clk_en) begin
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if (i_bus_is_data) begin
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/* do things with the bits...*/
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case (last_cmd)
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`BUSCMD_PC_READ:
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begin
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// o_bus_nibble_out <= rom_data[local_pc[`ROMBITS-1:0]];
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local_pc <= local_pc + 1;
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end
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`BUSCMD_DP_READ:
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begin
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// o_bus_nibble_out <= rom_data[local_dp[`ROMBITS-1:0]];
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local_dp <= local_dp + 1;
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end
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`BUSCMD_PC_WRITE: local_pc <= local_pc + 1;
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`BUSCMD_DP_WRITE: local_dp <= local_dp + 1;
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`BUSCMD_LOAD_PC:
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begin
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local_pc[addr_pos_ctr*4+:4] <= i_bus_nibble_in;
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addr_pos_ctr <= addr_pos_ctr + 1;
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end
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`BUSCMD_LOAD_DP:
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begin
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local_dp[addr_pos_ctr*4+:4] <= i_bus_nibble_in;
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addr_pos_ctr <= addr_pos_ctr + 1;
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end
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default: begin end
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endcase
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/* auto switch to pc read / dp read */
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if (addr_pos_ctr == 4) begin
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case (last_cmd)
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`BUSCMD_LOAD_PC: last_cmd <= `BUSCMD_PC_READ;
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`BUSCMD_LOAD_DP: last_cmd <= `BUSCMD_DP_READ;
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default: begin end
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endcase
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end
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`ifdef SIM
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$write("ROM-GX-R %0d: [%d] ", i_phase, i_cycle_ctr);
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case (last_cmd)
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`BUSCMD_PC_READ: $write("PC_READ <= rom[%5h]: %h", local_pc, imm_nibble);
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`BUSCMD_DP_READ: $write("DP_READ <= rom[%5h]: %h", local_dp, imm_nibble);
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`BUSCMD_LOAD_PC: $write("LOAD_PC - pc %5h, %h pos %0d", local_pc, i_bus_nibble_in, addr_pos_ctr);
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`BUSCMD_LOAD_DP: $write("LOAD_DP - dp %5h, %h pos %0d", local_dp, i_bus_nibble_in, addr_pos_ctr);
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`BUSCMD_CONFIGURE: $write("CONFIGURE - rom is not configurable");
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default: $write("last_command %h nibble %h - UNHANDLED", last_cmd, i_bus_nibble_in);
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endcase
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if (addr_pos_ctr == 4) begin
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case (last_cmd)
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`BUSCMD_LOAD_PC: $write(" auto switch to PC_READ");
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`BUSCMD_LOAD_DP: $write(" auto switch to DP_READ");
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default: begin end
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endcase
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end
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$write("\n");
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`endif
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end else begin
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last_cmd <= i_bus_nibble_in;
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if ((i_bus_nibble_in == `BUSCMD_LOAD_PC) || (i_bus_nibble_in == `BUSCMD_LOAD_DP))
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addr_pos_ctr <= 0;
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`ifdef SIM
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$write("ROM-GX-R %0d: [%d] ", i_phase, i_cycle_ctr);
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case (i_bus_nibble_in)
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`BUSCMD_PC_READ: $write("PC_READ");
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`BUSCMD_LOAD_PC: $write("LOAD_PC");
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`BUSCMD_LOAD_DP: $write("LOAD_DP");
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`BUSCMD_CONFIGURE: $write("CONFIGURE");
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`BUSCMD_RESET: $write("RESET");
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default: begin end
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endcase
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$write("\n");
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`endif
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end
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end
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if (i_reset) begin
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last_cmd <= 4'b0;
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addr_pos_ctr <= 3'b0;
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local_pc <= 20'b0;
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local_dp <= 20'b0;
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end
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end
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endmodule
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