mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
eeb5150159
fix bad maths in the rom-gx-r module wire in the PC in the debugger and the control unit add an execute flag, to start execution of partially decoded instructions that need reading data from the instruction stream
106 lines
No EOL
2.4 KiB
Verilog
106 lines
No EOL
2.4 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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module saturn_regs_pc_rstk (
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i_clk,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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i_debug_cycle,
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i_bus_busy,
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i_nibble,
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o_current_pc
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_debug_cycle;
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input wire [0:0] i_bus_busy;
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input wire [3:0] i_nibble;
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output wire [19:0] o_current_pc;
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/**************************************************************************************************
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*
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* pc and rstk handling module
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*
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*************************************************************************************************/
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/*
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* local variables
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*/
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reg [0:0] just_reset;
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reg [19:0] PC;
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assign o_current_pc = PC;
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initial begin
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just_reset = 1'b1;
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PC = 20'h00000;
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end
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/*
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* the process
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*/
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always @(posedge i_clk) begin
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/*
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* only do something when nothing is busy doing some other tasks
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* either talking to the bus, or debugging something
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*/
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// if (!i_debug_cycle)
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// $display("PC_RSTK %0d: [%d] !i_bus_busy %b", i_phase, i_cycle_ctr, !i_bus_busy);
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if (!i_debug_cycle && !i_bus_busy) begin
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if (i_phases[3] && just_reset) begin
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$display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);
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just_reset <= 1'b0;
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end
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if (i_phases[1] && !just_reset) begin
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$display("PC_RSTK %0d: [%d] inc_pc %5h => %5h", i_phase, i_cycle_ctr, PC, PC + 20'h00001);
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PC <= PC + 20'h00001;
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end
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end
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if (i_reset) begin
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just_reset <= 1'b1;
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PC <= 20'h00000;
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end
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end
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endmodule |