mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
506 lines
16 KiB
Verilog
506 lines
16 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`include "saturn_def_buscmd.v"
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`include "saturn_def_alu.v"
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module saturn_control_unit (
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i_clk,
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i_clk_en,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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i_bus_busy,
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o_program_data,
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o_program_address,
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i_program_address,
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o_no_read,
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i_nibble,
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o_error,
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/* debugger interface */
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o_current_pc,
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o_reg_alu_mode,
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o_reg_p,
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o_reg_hst,
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o_reg_st,
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/* register access */
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i_dbg_register,
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i_dbg_reg_ptr,
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o_dbg_reg_nibble,
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i_dbg_rstk_ptr,
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o_dbg_rstk_val,
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o_reg_rstk_ptr,
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o_alu_reg_dest,
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o_alu_reg_src_1,
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o_alu_reg_src_2,
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o_alu_imm_value,
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o_alu_opcode,
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o_instr_type,
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o_instr_decoded
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_bus_busy;
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output wire [4:0] o_program_data;
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output wire [4:0] o_program_address;
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input wire [4:0] i_program_address;
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output reg [0:0] o_no_read;
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input wire [3:0] i_nibble;
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output wire [0:0] o_error;
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assign o_error = control_unit_error || dec_error;
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/* debugger interface */
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output wire [19:0] o_current_pc;
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output wire [0:0] o_reg_alu_mode;
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assign o_reg_alu_mode = reg_alu_mode;
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output wire [3:0] o_reg_p;
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output wire [3:0] o_reg_hst;
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output wire [15:0] o_reg_st;
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/* register access */
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input wire [4:0] i_dbg_register;
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input wire [3:0] i_dbg_reg_ptr;
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output reg [3:0] o_dbg_reg_nibble;
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input wire [2:0] i_dbg_rstk_ptr;
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output wire [19:0] o_dbg_rstk_val;
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output wire [2:0] o_reg_rstk_ptr;
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output wire [4:0] o_alu_reg_dest;
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output wire [4:0] o_alu_reg_src_1;
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output wire [4:0] o_alu_reg_src_2;
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output wire [3:0] o_alu_imm_value;
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output wire [4:0] o_alu_opcode;
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output wire [3:0] o_instr_type;
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output wire [0:0] o_instr_decoded;
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assign o_current_pc = reg_PC;
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assign o_reg_p = reg_P;
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assign o_reg_hst = reg_HST;
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assign o_reg_st = reg_ST;
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assign o_alu_reg_dest = dec_alu_reg_dest;
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assign o_alu_reg_src_1 = dec_alu_reg_src_1;
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assign o_alu_reg_src_2 = dec_alu_reg_src_2;
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assign o_alu_imm_value = dec_alu_imm_value;
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assign o_alu_opcode = dec_alu_opcode;
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assign o_instr_type = dec_instr_type;
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assign o_instr_decoded = dec_instr_decoded;
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/**************************************************************************************************
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*
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* decoder module
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*
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*************************************************************************************************/
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saturn_inst_decoder instruction_decoder(
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.i_clk (i_clk),
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.i_clk_en (i_clk_en),
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.i_reset (i_reset),
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.i_phases (i_phases),
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.i_phase (i_phase),
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.i_cycle_ctr (i_cycle_ctr),
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.i_bus_busy (i_bus_busy),
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.i_nibble (i_nibble),
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.i_reg_p (reg_P),
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.i_current_pc (reg_PC),
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.o_alu_reg_dest (dec_alu_reg_dest),
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.o_alu_reg_src_1 (dec_alu_reg_src_1),
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.o_alu_reg_src_2 (dec_alu_reg_src_2),
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.o_alu_ptr_begin (dec_alu_ptr_begin),
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.o_alu_ptr_end (dec_alu_ptr_end),
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.o_alu_imm_value (dec_alu_imm_value),
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.o_alu_opcode (dec_alu_opcode),
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.o_jump_length (dec_jump_length),
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.o_instr_type (dec_instr_type),
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.o_push_pc (dec_push_pc),
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.o_instr_decoded (dec_instr_decoded),
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.o_instr_execute (dec_instr_execute),
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.o_decoder_error (dec_error)
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);
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wire [4:0] dec_alu_reg_dest;
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wire [4:0] dec_alu_reg_src_1;
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wire [4:0] dec_alu_reg_src_2;
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wire [3:0] dec_alu_ptr_begin;
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wire [3:0] dec_alu_ptr_end;
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wire [3:0] dec_alu_imm_value;
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wire [4:0] dec_alu_opcode;
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wire [2:0] dec_jump_length;
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wire [3:0] dec_instr_type;
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wire [0:0] dec_push_pc;
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wire [0:0] dec_instr_decoded;
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wire [0:0] dec_instr_execute;
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wire [0:0] dec_error;
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/*
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* wires for decode shortcuts
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*/
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wire [0:0] inst_alu = (dec_instr_type == `INSTR_TYPE_ALU);
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wire [0:0] inst_jump = (dec_instr_type == `INSTR_TYPE_JUMP);
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wire [0:0] reg_dest_c = (dec_alu_reg_dest == `ALU_REG_C);
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wire [0:0] reg_dest_hst = (dec_alu_reg_dest == `ALU_REG_HST);
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wire [0:0] reg_dest_st = (dec_alu_reg_dest == `ALU_REG_ST);
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wire [0:0] reg_dest_p = (dec_alu_reg_dest == `ALU_REG_P);
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wire [0:0] reg_src_1_p = (dec_alu_reg_src_1 == `ALU_REG_P);
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wire [0:0] reg_src_1_imm = (dec_alu_reg_src_1 == `ALU_REG_IMM);
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wire [0:0] aluop_copy = inst_alu && (dec_alu_opcode == `ALU_OP_COPY);
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wire [0:0] aluop_clr_mask = inst_alu && (dec_alu_opcode == `ALU_OP_CLR_MASK);
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wire [0:0] inst_alu_p_eq_n = aluop_copy && reg_dest_p && reg_src_1_imm;
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wire [0:0] inst_alu_c_eq_p_n = aluop_copy && reg_dest_c && reg_src_1_p;
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wire [0:0] inst_alu_clrhst_n = aluop_clr_mask && reg_dest_hst && reg_src_1_imm;
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wire [0:0] inst_alu_st_eq_01_n = aluop_copy && reg_dest_st && reg_src_1_imm;
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wire [0:0] inst_alu_other = !(inst_alu_p_eq_n ||
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inst_alu_st_eq_01_n ||
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inst_alu_c_eq_p_n);
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/**************************************************************************************************
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*
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* registers module (contains A, B, C, D, R0, R1, R2, R3, R4)
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*
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*************************************************************************************************/
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/**************************************************************************************************
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*
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* PC and RSTK module
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*
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*************************************************************************************************/
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saturn_regs_pc_rstk regs_pc_rstk (
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.i_clk (i_clk),
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.i_clk_en (i_clk_en),
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.i_reset (i_reset),
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.i_phases (i_phases),
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.i_phase (i_phase),
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.i_cycle_ctr (i_cycle_ctr),
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.i_bus_busy (i_bus_busy),
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.i_nibble (i_nibble),
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.i_jump_instr (inst_jump),
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.i_jump_length (dec_jump_length),
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.i_push_pc (dec_push_pc),
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.o_current_pc (reg_PC),
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.o_reload_pc (reload_PC),
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.i_dbg_rstk_ptr (i_dbg_rstk_ptr),
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.o_dbg_rstk_val (o_dbg_rstk_val),
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.o_reg_rstk_ptr (o_reg_rstk_ptr)
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);
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/**************************************************************************************************
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*
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* other processor registers
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*
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*************************************************************************************************/
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reg [0:0] reg_alu_mode;
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reg [3:0] reg_C[0:15];
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reg [3:0] reg_HST;
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reg [15:0] reg_ST;
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reg [3:0] reg_P;
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wire [19:0] reg_PC;
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wire [0:0] reload_PC;
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always @(i_dbg_register, i_dbg_reg_ptr) begin
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case (i_dbg_register)
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`ALU_REG_C: o_dbg_reg_nibble <= reg_C[i_dbg_reg_ptr];
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default: o_dbg_reg_nibble <= 4'h0;
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endcase
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end
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/**************************************************************************************************
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*
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* the control unit
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*
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*************************************************************************************************/
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reg [0:0] control_unit_error;
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reg [0:0] just_reset;
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reg [3:0] init_counter;
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reg [0:0] control_unit_ready;
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reg [4:0] bus_program[0:31];
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reg [4:0] bus_prog_addr;
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reg [2:0] addr_nibble_ptr;
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reg [0:0] load_pc_loop;
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reg [0:0] send_pc_read;
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wire [3:0] reg_PC_nibble = reg_PC[addr_nibble_ptr*4+:4];
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assign o_program_data = bus_program[i_program_address];
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assign o_program_address = bus_prog_addr;
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initial begin
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/* control variables */
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o_no_read = 1'b0;
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control_unit_error = 1'b0;
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just_reset = 1'b1;
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init_counter = 4'b0;
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control_unit_ready = 1'b0;
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bus_prog_addr = 5'd0;
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addr_nibble_ptr = 3'd0;
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load_pc_loop = 1'b0;
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/* registers */
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reg_alu_mode = 1'b0;
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reg_HST = 4'b0;
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reg_ST = 16'b0;
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reg_P = 4'b0;
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end
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always @(posedge i_clk) begin
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if (just_reset || (init_counter != 0)) begin
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$display("CTRL %0d: [%d] initializing registers %0d", i_phase, i_cycle_ctr, init_counter);
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reg_C[init_counter] <= 4'h0;
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init_counter <= init_counter + 4'b1;
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end
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/************************
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*
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* we're just starting, load the PC into the controller and modules
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* this could also be used when loading the PC on jumps, need to identify conditions
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*
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*/
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if (i_clk_en && (just_reset || reload_PC) && i_phases[3]) begin
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/* this happend right after reset */
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if (just_reset) begin
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`ifdef SIM
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$display("CTRL %0d: [%d] we were just reset, loading PC", i_phase, i_cycle_ctr);
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`endif
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just_reset <= 1'b0;
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end else begin
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`ifdef SIM
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$display("CTRL %0d: [%d] reloading PC", i_phase, i_cycle_ctr);
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`endif
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end
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/* this loads the PC to the modules */
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_LOAD_PC };
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`ifdef SIM
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$display("CTRL %0d: [%d] pushing LOAD_PC command to pos %d", i_phase, i_cycle_ctr, bus_prog_addr);
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`endif
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addr_nibble_ptr <= 3'b0;
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bus_prog_addr <= bus_prog_addr + 5'd1;
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load_pc_loop <= 1'b1;
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end
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/* loop to fill the initial PC value in the program */
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if (i_clk_en && load_pc_loop) begin
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/*
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* this should load the actual PC values...
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*/
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bus_program[bus_prog_addr] <= {1'b0, reg_PC_nibble };
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addr_nibble_ptr <= addr_nibble_ptr + 3'd1;
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bus_prog_addr <= bus_prog_addr + 5'd1;
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`ifdef SIM
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if (addr_nibble_ptr == 3'd0)
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$display("CTRL %0d: [%d] new PC value %5h", i_phase, i_cycle_ctr, reg_PC);
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$write("CTRL %0d: [%d] pushing ADDR : prog[%2d] <= PC[%0d] (%h)", i_phase, i_cycle_ctr,
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bus_prog_addr, addr_nibble_ptr, {1'b0, reg_PC_nibble });
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`endif
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if (addr_nibble_ptr == 3'd4) begin
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load_pc_loop <= 1'b0;
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control_unit_ready <= 1'b1;
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`ifdef SIM
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$write(" done");
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`endif
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end
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`ifdef SIM
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$write("\n");
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`endif
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end
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/************************
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*
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* main execution loop
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*
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*/
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if (i_clk_en && control_unit_ready && !i_bus_busy) begin
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// `ifdef SIM
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// $display("CTRL %0d: [%d] starting to do things", i_phase, i_cycle_ctr);
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// `endif
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// if (i_phases[2]) begin
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// $display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
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// end
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if (i_phases[3] && dec_instr_execute) begin
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case (dec_instr_type)
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`INSTR_TYPE_NOP: begin
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$display("CTRL %0d: [%d] NOP instruction", i_phase, i_cycle_ctr);
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end
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`INSTR_TYPE_ALU: begin
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$display("CTRL %0d: [%d] ALU instruction", i_phase, i_cycle_ctr);
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/*
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* treat special cases
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*/
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/* 2n P= n */
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if (inst_alu_p_eq_n) begin
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$display("CTRL %0d: [%d] exec : P= %h", i_phase, i_cycle_ctr, dec_alu_imm_value);
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reg_P <= dec_alu_imm_value;
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end
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/* 80Cn C=P n */
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if (inst_alu_c_eq_p_n) begin
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reg_C[dec_alu_ptr_begin] <= reg_P;
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end
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if (inst_alu_clrhst_n) begin
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`ifdef SIM
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$write("CTRL %0d: [%d] exec : ", i_phase, i_cycle_ctr);
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case (dec_alu_imm_value)
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4'h1: $display("XM=0");
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4'h2: $display("SB=0");
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4'h4: $display("SR=0");
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4'h8: $display("MP=0");
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4'hF: $display("CLRHST");
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default: $display("CLRHST %h", dec_alu_imm_value);
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endcase
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`endif
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reg_HST = reg_HST & ~dec_alu_imm_value;
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end
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/* 8[45]n ST=[01] n */
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if (inst_alu_st_eq_01_n) begin
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$display("CTRL %0d: [%d] exec : ST=%b %h", i_phase, i_cycle_ctr, dec_alu_imm_value[0], dec_alu_ptr_begin);
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reg_ST[dec_alu_ptr_begin] <= dec_alu_imm_value[0];
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end
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/*
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* the general case
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*/
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end
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`INSTR_TYPE_SET_MODE :
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begin
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`ifdef SIM
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$write("CTRL %0d: [%d] exec : ", i_phase, i_cycle_ctr);
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case (dec_alu_imm_value)
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4'h0: $display("SETHEX");
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4'h1: $display("SETDEC");
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default: begin end /* does not exist */
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endcase
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`endif
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reg_alu_mode <= dec_alu_imm_value[0];
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end
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`INSTR_TYPE_JUMP: begin end
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`INSTR_TYPE_LOAD:
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begin
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case (dec_alu_reg_dest)
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`ALU_REG_A: begin end
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`ALU_REG_C:
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begin
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$display("CTRL %0d: [%d] C[%2d] <= %h", i_phase, i_cycle_ctr, dec_alu_ptr_begin, dec_alu_imm_value);
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reg_C[dec_alu_ptr_begin] <= dec_alu_imm_value;
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end
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default: $display("CTRL %0d: [%d] unsupported register for load %0d", i_phase, i_cycle_ctr, dec_alu_reg_dest);
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endcase
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end
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`INSTR_TYPE_RESET:
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begin
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$display("CTRL %0d: [%d] exec : RESET", i_phase, i_cycle_ctr);
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_RESET };
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bus_prog_addr <= bus_prog_addr + 5'd1;
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send_pc_read <= 1'b1;
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end
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default:
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begin
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$display("CTRL %0d: [%d] unsupported instruction", i_phase, i_cycle_ctr);
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end
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endcase
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end
|
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if (send_pc_read) begin
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$display("CTRL %0d: [%d] exec : RESET - send PC_READ", i_phase, i_cycle_ctr);
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_PC_READ };
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bus_prog_addr <= bus_prog_addr + 5'd1;
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send_pc_read <= 1'b0;
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|
end
|
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end
|
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|
|
if (i_reset) begin
|
|
/* control variables */
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|
o_no_read <= 1'b0;
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|
control_unit_error <= 1'b0;
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|
just_reset <= 1'b1;
|
|
init_counter <= 4'b0;
|
|
control_unit_ready <= 1'b0;
|
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bus_prog_addr <= 5'd0;
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addr_nibble_ptr <= 3'd0;
|
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load_pc_loop <= 1'b0;
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|
|
|
/* registers */
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reg_alu_mode <= 1'b0;
|
|
reg_HST <= 4'b0;
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reg_ST <= 16'b0;
|
|
reg_P <= 4'b0;
|
|
end
|
|
|
|
end
|
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endmodule
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