mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
eeb5150159
fix bad maths in the rom-gx-r module wire in the PC in the debugger and the control unit add an execute flag, to start execution of partially decoded instructions that need reading data from the instruction stream
245 lines
No EOL
7.1 KiB
Verilog
245 lines
No EOL
7.1 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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module saturn_bus_controller (
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i_clk,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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o_bus_clk_en,
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o_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in,
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o_debug_cycle,
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o_halt
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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output reg [0:0] o_bus_clk_en;
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output reg [0:0] o_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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output wire [0:0] o_debug_cycle;
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output wire [0:0] o_halt;
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/**************************************************************************************************
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*
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* master control unit
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*
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*************************************************************************************************/
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saturn_control_unit control_unit (
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.i_clk (i_clk),
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.i_reset (i_reset),
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.i_phases (i_phases),
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.i_phase (i_phase),
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.i_cycle_ctr (i_cycle_ctr),
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.i_debug_cycle (dbg_debug_cycle),
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.i_bus_busy (bus_busy),
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.o_program_address (ctrl_unit_prog_addr),
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.i_program_address (bus_prog_addr),
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.o_program_data (ctrl_unit_prog_data),
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.o_no_read (ctrl_unit_no_read),
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.i_nibble (i_bus_nibble_in),
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.o_error (ctrl_unit_error),
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/* debugger interface */
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.o_current_pc (ctrl_current_pc),
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.o_alu_reg_dest (dec_alu_reg_dest),
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.o_alu_reg_src_1 (dec_alu_reg_src_1),
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.o_alu_reg_src_2 (dec_alu_reg_src_2),
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.o_alu_imm_value (dec_alu_imm_value),
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.o_alu_opcode (dec_alu_opcode),
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.o_instr_type (dec_instr_type),
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.o_instr_decoded (dec_instr_decoded)
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);
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wire [0:0] ctrl_unit_error;
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wire [4:0] ctrl_unit_prog_addr;
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wire [4:0] ctrl_unit_prog_data;
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wire [0:0] ctrl_unit_no_read;
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/* debugger insterface */
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wire [19:0] ctrl_current_pc;
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wire [4:0] dec_alu_reg_dest;
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wire [4:0] dec_alu_reg_src_1;
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wire [4:0] dec_alu_reg_src_2;
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wire [3:0] dec_alu_imm_value;
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wire [4:0] dec_alu_opcode;
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wire [3:0] dec_instr_type;
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wire [0:0] dec_instr_decoded;
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/**************************************************************************************************
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*
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* debugger module
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*
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*************************************************************************************************/
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saturn_debugger debugger (
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.i_clk (i_clk),
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.i_reset (i_reset),
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.i_phases (i_phases),
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.i_phase (i_phase),
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.i_cycle_ctr (i_cycle_ctr),
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.o_debug_cycle (dbg_debug_cycle),
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/* debugger interface */
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.i_current_pc (ctrl_current_pc),
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.i_alu_reg_dest (dec_alu_reg_dest),
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.i_alu_reg_src_1 (dec_alu_reg_src_1),
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.i_alu_reg_src_2 (dec_alu_reg_src_2),
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.i_alu_imm_value (dec_alu_imm_value),
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.i_alu_opcode (dec_alu_opcode),
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.i_instr_type (dec_instr_type),
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.i_instr_decoded (dec_instr_decoded)
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);
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wire [0:0] dbg_debug_cycle;
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assign o_debug_cycle = dbg_debug_cycle;
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/**************************************************************************************************
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*
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* the bus controller module
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*
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*************************************************************************************************/
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/*
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* local registers
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*/
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reg [0:0] bus_error;
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reg [0:0] bus_busy;
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/*
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* program list for the bus controller
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* this is used for the control unit to send the bus controller
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* the list of things that need to be done for long sequences
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*/
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reg [4:0] bus_prog_addr;
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wire [0:0] more_to_write;
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assign more_to_write = (bus_prog_addr != ctrl_unit_prog_addr);
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/*
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* this should come from the debugger
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*/
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assign o_halt = bus_error || ctrl_unit_error;
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initial begin
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bus_error = 1'b0;
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bus_prog_addr = 5'd0;
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bus_busy = 1'b1;
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end
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/*
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* bus chronograms
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*
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* The bus works on a 4 phase system
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*
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*/
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always @(posedge i_clk) begin
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if (!o_debug_cycle) begin
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case (i_phases)
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4'b0001:
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begin
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/*
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* in this phase, we can send a command or data from the processor
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*/
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// $display("BUSCTRL %0d: [%d] cycle start", i_phase, i_cycle_ctr);
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if (more_to_write) begin
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$write("BUSCTRL %0d: [%d] %0d|%0d : %5b ", i_phase, i_cycle_ctr,
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bus_prog_addr, ctrl_unit_prog_addr, ctrl_unit_prog_data);
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if (ctrl_unit_prog_data[4]) $write("CMD : ");
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else $write("DATA : ");
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$write("%h\n", ctrl_unit_prog_data[3:0]);
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bus_prog_addr <= bus_prog_addr + 5'b1;
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o_bus_is_data <= !ctrl_unit_prog_data[4];
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o_bus_nibble_out <= ctrl_unit_prog_data[3:0];
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o_bus_clk_en <= 1'b1;
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bus_busy <= 1'b1;
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end
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/*
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* nothing to send, see if we can read, and do it
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*/
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if (!more_to_write && !ctrl_unit_no_read) begin
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// $display("BUSCTRL %0d: [%d] setting up read", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b1;
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end
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end
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4'b0010:
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begin
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/*
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* this phase is reserved for reading data from the bus
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*/
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if (o_bus_clk_en) begin
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// $display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b0;
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end
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end
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4'b0100:
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begin
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/*
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* this phase is when the instruction decoder does it's job
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*/
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if (!more_to_write && bus_busy) begin
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$display("BUSCTRL %0d: [%d] done sending the entire program", i_phase, i_cycle_ctr);
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bus_busy <= 1'b0;
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end
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end
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4'b1000:
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begin
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/*
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* instructions that can be handled in one clock are done here, otherwise, we start the ALU
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*/
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end
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default: begin end // other states should not exist
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endcase
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end
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if (i_reset) begin
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bus_error <= 1'b0;
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bus_prog_addr <= 5'd0;
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bus_busy <= 1'b1;
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end
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end
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endmodule |