mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-19 10:26:58 +01:00
66 lines
1.1 KiB
Verilog
66 lines
1.1 KiB
Verilog
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`include "bus_commands.v"
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`include "hp48_rom.v"
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`include "hp48_io_ram.v"
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`ifndef _HP48_BUS
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`define _HP48_BUS
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/**************************************************************************************************
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*
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* Bus manager
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*
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*
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*
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*/
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module hp48_bus (
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input strobe,
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input reset,
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input [19:0] address,
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input [3:0] command,
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input [3:0] nibble_in,
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output reg [3:0] nibble_out,
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output reg bus_error
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);
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// io_ram
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wire [3:0] io_ram_nibble_out;
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wire io_ram_active;
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wire io_ram_error;
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// rom
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wire [3:0] rom_nibble_out;
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//
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// listed in order of priority
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//
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hp48_io_ram dev_io_ram (
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.strobe (strobe),
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.reset (reset),
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.address (address),
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.command (command),
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.nibble_in (nibble_in),
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.nibble_out (io_ram_nibble_out),
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.io_ram_active (io_ram_active),
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.io_ram_error (io_ram_error)
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);
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hp48_rom dev_rom (
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.strobe (strobe),
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.address (address),
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.command (command),
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.nibble_out (rom_nibble_out)
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);
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always @(*)
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begin
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bus_error = io_ram_error;
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if (io_ram_active) nibble_out = io_ram_nibble_out;
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if (!io_ram_active) nibble_out = rom_nibble_out;
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end
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endmodule
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`endif
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