mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
205 lines
No EOL
5.2 KiB
Verilog
205 lines
No EOL
5.2 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`ifndef _SATURN_DECODER_BLOCK_VARS
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`define _SATURN_DECODER_BLOCK_VARS
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/*
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*
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* Block vars registers
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*
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*/
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reg block_0x;
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wire do_block_0x;
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assign do_block_0x = do_on_other_nibbles && block_0x;
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reg block_0Efx;
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wire do_block_0Efx;
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assign do_block_0Efx = do_on_other_nibbles && block_0Efx;
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reg block_1x;
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wire do_block_1x;
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assign do_block_1x = do_on_other_nibbles && block_1x;
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reg block_save_to_R_W;
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wire do_block_save_to_R_W;
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assign do_block_save_to_R_W = do_on_other_nibbles && block_save_to_R_W;
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reg block_rest_from_R_W;
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wire do_block_rest_from_R_W;
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assign do_block_rest_from_R_W = do_on_other_nibbles && block_rest_from_R_W;
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reg block_exch_with_R_W;
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wire do_block_exch_with_R_W;
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assign do_block_exch_with_R_W = do_on_other_nibbles && block_exch_with_R_W;
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wire do_block_Rn_A_C;
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assign do_block_Rn_A_C = do_on_other_nibbles &&
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( block_save_to_R_W ||
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block_rest_from_R_W ||
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block_exch_with_R_W );
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reg block_13x;
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wire do_block_13x;
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assign do_block_13x = do_on_other_nibbles && block_13x;
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reg block_14x_15xx;
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wire do_block_14x_15xx;
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assign do_block_14x_15xx = do_on_other_nibbles && block_14x_15xx;
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reg block_15xx;
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wire do_block_15xx;
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assign do_block_15xx = do_on_other_nibbles && block_15xx;
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reg block_pointer_arith_const;
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wire do_block_pointer_arith_const;
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assign do_block_pointer_arith_const = do_on_other_nibbles && block_pointer_arith_const;
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reg block_2x;
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wire do_block_2x;
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assign do_block_2x = do_on_other_nibbles && block_2x;
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reg block_3x;
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wire do_block_3x;
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assign do_block_3x = do_on_other_nibbles && block_3x;
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reg block_8x;
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wire do_block_8x;
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assign do_block_8x = do_on_other_nibbles && block_8x;
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reg block_80x;
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wire do_block_80x;
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assign do_block_80x = do_on_other_nibbles && block_80x;
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reg block_80Cx;
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wire do_block_80Cx;
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assign do_block_80Cx = do_on_other_nibbles && block_80Cx;
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reg block_81x;
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wire do_block_81x;
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assign do_block_81x = do_on_other_nibbles && block_81x;
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reg block_81Ax;
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wire do_block_81Ax;
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assign do_block_81Ax = do_on_other_nibbles && block_81Ax;
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reg block_81Af0x;
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wire do_block_81Af0x;
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assign do_block_81Af0x = do_on_other_nibbles && block_81Af0x;
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reg block_81Af1x;
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wire do_block_81Af1x;
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assign do_block_81Af1x = do_on_other_nibbles && block_81Af1x;
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reg block_81Af2x;
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wire do_block_81Af2x;
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assign do_block_81Af2x = do_on_other_nibbles && block_81Af2x;
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reg block_81Afx;
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wire do_block_81Afx;
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assign do_block_81Afx = do_on_other_nibbles && block_81Afx;
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reg block_82x;
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wire do_block_82x;
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assign do_block_82x = do_on_other_nibbles && block_82x;
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reg block_84x_85x;
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wire do_block_84x_85x;
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assign do_block_84x_85x = do_on_other_nibbles && block_84x_85x;
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reg block_8Ax;
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wire do_block_8Ax;
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assign do_block_8Ax = do_on_other_nibbles && block_8Ax;
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reg block_jump_test;
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reg block_jump_test2;
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wire do_block_jump_test;
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wire do_block_jump_test2;
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assign do_block_jump_test = do_on_other_nibbles && block_jump_test;
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assign do_block_jump_test2 = do_on_other_nibbles && block_jump_test2;
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reg block_9x;
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wire do_block_9x;
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assign do_block_9x = do_on_other_nibbles && block_9x;
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reg block_9ax;
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wire do_block_9ax;
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assign do_block_9ax = do_on_other_nibbles && block_9ax;
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reg block_9bx;
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wire do_block_9bx;
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assign do_block_9bx = do_on_other_nibbles && block_9bx;
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reg block_Ax;
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wire do_block_Ax;
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assign do_block_Ax = do_on_other_nibbles && block_Ax;
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reg block_Aax;
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wire do_block_Aax;
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assign do_block_Aax = do_on_other_nibbles && block_Aax;
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reg block_Abx;
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wire do_block_Abx;
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assign do_block_Abx = do_on_other_nibbles && block_Abx;
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reg block_Bx;
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wire do_block_Bx;
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assign do_block_Bx = do_on_other_nibbles && block_Bx;
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reg block_Bax;
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wire do_block_Bax;
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assign do_block_Bax = do_on_other_nibbles && block_Bax;
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reg block_Bbx;
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wire do_block_Bbx;
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assign do_block_Bbx = do_on_other_nibbles && block_Bbx;
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reg block_Cx;
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wire do_block_Cx;
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assign do_block_Cx = do_on_other_nibbles && block_Cx;
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reg block_Dx;
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wire do_block_Dx;
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assign do_block_Dx = do_on_other_nibbles && block_Dx;
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reg block_Fx;
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wire do_block_Fx;
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assign do_block_Fx = do_on_other_nibbles && block_Fx;
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reg go_fields_table;
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/*
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* subroutines
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*/
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reg block_load_reg_imm;
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wire do_load_reg_imm;
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assign do_load_reg_imm = do_on_other_nibbles && block_load_reg_imm;
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reg block_jmp;
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wire do_block_jmp;
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assign do_block_jmp = do_on_other_nibbles && block_jmp;
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wire in_fields_table;
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assign in_fields_table = go_fields_table && !fields_table_done;
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`endif |