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https://github.com/sxpert/hp-saturn
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45 lines
1.2 KiB
Verilog
45 lines
1.2 KiB
Verilog
`include "decstates.v"
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case (decstate)
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`DEC_ALU_INIT, `DEC_ALU_CONT: begin
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`ifdef SIM
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if (alu_debug) begin
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$display("----------------------- z_alu_phase_2 - Do calculations ------------------------");
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$display("data received from reading : %h", bus_nibble_out);
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end
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`endif
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case (alu_op)
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`ALU_OP_ZERO: begin
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alu_res1 <= 0;
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alu_res_carry <= 0;
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end
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`ALU_OP_COPY: begin
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alu_res1 <= (alu_reg_src1 == `ALU_REG_M)? bus_nibble_out : alu_src1;
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alu_res_carry <= 0;
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end
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`ALU_OP_EXCH: begin
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alu_res1 <= alu_src2;
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alu_res2 <= alu_src1;
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alu_res_carry <= 0;
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end
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`ALU_OP_2CMPL: begin
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{alu_res_carry, alu_res1} <= ~alu_src1 + alu_carry;
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end
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`ALU_OP_1CMPL: begin
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alu_res1 <= ~alu_src1;
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alu_res_carry <= 0;
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end
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`ALU_OP_INC: begin
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{alu_res_carry, alu_res1} <= alu_src1 + alu_carry;
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end
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`ALU_OP_TEST_EQ: begin
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alu_res_carry <= (alu_src1 == alu_src2) & alu_carry;
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end
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`ALU_OP_TEST_NEQ: begin
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alu_res_carry <= (alu_src1 != alu_src2) & alu_carry;
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end
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default: $display("ALU PHASE 2 ERROR : unknown op %d", alu_op);
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endcase
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end
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endcase
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