mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-31 19:57:50 +01:00
58 lines
No EOL
1.5 KiB
Verilog
58 lines
No EOL
1.5 KiB
Verilog
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/******************************************************************************
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* A[ab]x
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*
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* lots of things there
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*
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*/
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`include "decstates.v"
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`include "fields.v"
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`DEC_Axx_EXEC: begin
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if (!field_table[0]) begin
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$display("table 'a' not handled yet");
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decode_error <= 1;
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end else begin
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if (!nb_in[3]) begin
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alu_reg_dest <= {2'b0, nb_in[1:0]};
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if (!nb_in[2]) alu_op <= `ALU_OP_ZERO;
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else begin
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alu_op <= `ALU_OP_COPY;
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alu_reg_src1 <= {2'b00, nb_in[0], (!(nb_in[0] | nb_in[1])) & nb_in[2]};
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end;
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end else begin
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$display("DEC_Axx_EXEC %h", nb_in);
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decode_error <= 1;
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end
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end
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alu_debug <= 1;
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next_cycle <= `BUSCMD_NOP;
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decstate <= `DEC_ALU_INIT;
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alu_return <= `DEC_START;
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`ifdef SIM
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$write("%5h ", inst_start_PC);
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if (!nb_in[3])
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case (nb_in[1:0])
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2'b00: $write("A=%s",(!nb_in[2])?"0":"B");
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2'b01: $write("B=%s",(!nb_in[2])?"0":"C");
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2'b10: $write("C=%s",(!nb_in[2])?"0":"A");
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2'b11: $write("D=%s",(!nb_in[2])?"0":"C");
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endcase
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else begin
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$write("NOT HANDLED");
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end
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$write("\t");
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case (field)
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`T_FIELD_P: $display("P");
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`T_FIELD_WP: $display("WP");
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`T_FIELD_XS: $display("XS");
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`T_FIELD_X: $display("X");
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`T_FIELD_S: $display("S");
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`T_FIELD_M: $display("M");
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`T_FIELD_B: $display("B");
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`T_FIELD_W: $display("W");
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endcase
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`endif
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end |