mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
48 lines
No EOL
1.4 KiB
Verilog
48 lines
No EOL
1.4 KiB
Verilog
/******************************************************************************
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* 8
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* a lot of things start with 8...
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*
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*/
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`include "decstates.v"
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`DEC_8: begin
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case (nibble)
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4'hD: decstate <= `DEC_GOVLNG;
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4'hF: decstate <= `DEC_GOSBVL;
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default: begin end
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endcase
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end
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// DECODE_8:
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// case (runstate)
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// `RUN_DECODE: runstate <= `INSTR_START;
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// `INSTR_START, `INSTR_STROBE: begin end
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// `INSTR_READY:
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// begin
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// case (nibble)
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// 4'h0: decstate <= DECODE_80;
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// 4'h2: decstate <= DECODE_82;
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// 4'h4: decstate <= DECODE_ST_EQ_0_N;
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// 4'h5: decstate <= DECODE_ST_EQ_1_N;
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// 4'hd: decstate <= DECODE_GOVLNG;
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// 4'hf: decstate <= DECODE_GOSBVL;
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// default:
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// begin
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// `ifdef SIM
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// $display("unhandled instruction prefix 8%h", nibble);
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// `endif
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// decode_error <= 1;
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// end
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// endcase
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// runstate <= `RUN_DECODE;
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// end
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// default:
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// begin
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// `ifdef SIM
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// $display("DECODE_8: runstate %h", runstate);
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// `endif
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// decode_error <= 1;
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// end
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// endcase
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