mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
24 lines
496 B
Verilog
24 lines
496 B
Verilog
/******************************************************************************
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* 0X
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*
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*
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*/
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DECODE_0:
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begin
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if (runstate == `RUN_DECODE)
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runstate <= `INSTR_START;
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if (runstate == `INSTR_READY)
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case (nibble)
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4'h3: decstate <= DECODE_RTNCC;
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4'h4: decstate <= DECODE_SETHEX;
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4'h5: decstate <= DECODE_SETDEC;
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default:
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begin
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decode_error <= 1;
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`ifdef SIM
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$display("%05h 0%h => unimplemented", saved_PC, nibble);
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`endif
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end
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endcase
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end
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