mirror of
https://github.com/sxpert/hp-saturn
synced 2025-02-07 20:46:14 +01:00
28 lines
498 B
Verilog
28 lines
498 B
Verilog
/******************************************************************************
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* 0X
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*
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*
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*/
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`DEC_0X: begin
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case (nibble)
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4'h3:
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`include "opcodes/03_RTNCC.v"
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// execute_cycle <= 1;
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// decstate <= `DEC_RTNCC;
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4'h4: begin
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`include "opcodes/04_SETHEX.v"
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// execute_cycle <= 1;
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// decstate <= `DEC_SETHEX;
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end
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4'h5: begin
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execute_cycle <= 1;
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decstate <= `DEC_SETDEC;
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end
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default: begin
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$display("ERROR : DEC_0X");
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decode_error <= 1;
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end
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endcase
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end
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