mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
141 lines
3.2 KiB
Verilog
141 lines
3.2 KiB
Verilog
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//--------------------------------------------------------------------------------------------------
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//
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// bus control
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//
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//--------------------------------------------------------------------------------------------------
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`include "fields.v"
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`include "bus_commands.v"
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always @(posedge bus_ctrl_clk)
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begin
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if (!reset) begin
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if (clk3) begin
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en_dec_clk <= 0;
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if (cycle_ctr_ready)
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cycle_ctr <= cycle_ctr + 1;
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else cycle_ctr_ready <= 1;
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case (next_cycle)
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`BUSCMD_NOP: begin
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bus_command <= `BUSCMD_NOP;
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// $display("BUS NOT READING, STILL CLOCKING");
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end
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`BUSCMD_PC_READ: begin
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bus_command <= `BUSCMD_PC_READ;
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en_bus_clk <= 1;
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PC <= next_PC;
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inc_pc <= 1;
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end
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`BUSCMD_DP_READ: begin
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bus_command <= `BUSCMD_DP_READ;
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en_bus_clk <= 1;
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end
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`BUSCMD_DP_WRITE: begin
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bus_command <= `BUSCMD_DP_WRITE;
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bus_nibble_in <= nb_out;
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en_bus_clk <= 1;
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end
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`BUSCMD_LOAD_PC: begin
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bus_command <= `BUSCMD_LOAD_PC;
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bus_address <= new_PC;
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next_PC <= new_PC;
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PC <= new_PC;
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en_bus_clk <= 1;
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end
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`BUSCMD_LOAD_DP: begin
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bus_command <= `BUSCMD_LOAD_DP;
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bus_address <= add_out;
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en_bus_clk <= 1;
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end
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`BUSCMD_CONFIGURE: begin
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bus_command <= `BUSCMD_CONFIGURE;
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bus_address <= add_out;
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en_bus_clk <= 1;
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end
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`BUSCMD_RESET: begin
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bus_command <= `BUSCMD_RESET;
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en_bus_clk <= 1;
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end
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default: begin
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$display("BUS PHASE 1: %h UNIMPLEMENTED", next_cycle);
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end
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endcase
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end
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else begin
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case (next_cycle)
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`BUSCMD_NOP: begin
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en_dec_clk <= 1;
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end
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`BUSCMD_PC_READ: begin
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nb_in <= bus_nibble_out;
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en_dec_clk <= 1;
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if (inc_pc) begin
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next_PC <= PC + 1;
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inc_pc <= 0;
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end
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// $display("reading nibble %h", bus_nibble_out);
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end
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`BUSCMD_DP_READ: begin
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nb_in <= bus_nibble_out;
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en_dec_clk <= 1;
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end
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`BUSCMD_DP_WRITE: begin
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// $display("BUS PHASE 2: DP_WRITE cnt %h | ctr %h", t_cnt, t_ctr);
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en_dec_clk <= 1;
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end
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`BUSCMD_LOAD_PC: begin
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// $display("CYCLE %d | INSTR %d -> BUSCMD_LOAD_PC %5h", cycle_ctr, instr_ctr, new_PC);
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en_dec_clk <= 1;
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end
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`BUSCMD_LOAD_DP: begin
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// $display("CYCLE %d | INSTR %d -> BUSCMD_LOAD_DP %s %5h",
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// cycle_ctr, instr_ctr, t_ptr?"D1":"D0", add_out);
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en_dec_clk <= 1;
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end
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`BUSCMD_CONFIGURE: begin
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// $display("CYCLE %d | INSTR %d -> BUSCMD_CONFIGURE %5h", cycle_ctr, instr_ctr, add_out);
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en_dec_clk <= 1;
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end
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`BUSCMD_RESET: begin
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// $display("CYCLE %d | INSTR %d -> BUSCMD_RESET", cycle_ctr, instr_ctr);
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en_dec_clk <= 1;
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end
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default: begin
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$display("BUS PHASE 2: %h UNIMPLEMENTED", next_cycle);
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end
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endcase
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en_bus_clk <= 0;
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end
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end
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else begin
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$display("RESET");
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end
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end
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always @(posedge ph0) begin
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if (dbg_op_code)
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case (dbg_op_code)
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default: begin
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`ifdef SIM
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$display("DEBUGGER - UNKNOWN OPCODE: %4h", dbg_op_code);
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`endif
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end
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endcase
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`ifdef SIM
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else $display("DEBUGGER - NOTHING TO DO");
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`endif
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end
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always @(posedge ph1) begin
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`include "opcodes/z_alu_phase_1.v"
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end
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always @(posedge ph2) begin
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`include "opcodes/z_alu_phase_2.v"
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end
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always @(posedge ph3) begin
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if (cycle_ctr == 890)
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debug_stop <= 1;
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end
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