mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-31 19:57:50 +01:00
124 lines
3.2 KiB
Verilog
124 lines
3.2 KiB
Verilog
case (decstate)
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`DEC_ALU_INIT, `DEC_ALU_CONT: begin
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`ifdef SIM
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if (alu_debug) begin
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$display("------------------------------- z_alu_phase_2 ---------------------------------");
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$write("ALU OP ");
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case (alu_op)
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`ALU_OP_ZERO: $write("ZERO ");
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`ALU_OP_COPY: $write("COPY ");
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`ALU_OP_EXCH: $write("EXCH ");
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`ALU_OP_SHL: $write("SHL ");
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`ALU_OP_SHR: $write("SHR ");
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`ALU_OP_2CMPL: $write("2CMPL ");
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`ALU_OP_1CMPL: $write("1CMPL ");
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`ALU_OP_INC: $write("INC ");
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`ALU_OP_TEST_EQ: $write("TEST_EQ ");
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`ALU_OP_TEST_NEQ: $write("TEST_NEQ");
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endcase
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$display(" | FRST %h | LAST %h | SRC1 %h | SRC2 %h | DEST %h",
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alu_first, alu_last, alu_reg_src1, alu_reg_src2,alu_reg_dest);
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$display("CARRY %b | STICKY-BIT %b", Carry, HST[1]);
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case (alu_reg_dest)
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`ALU_REG_A: $display("A: %h", A);
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`ALU_REG_B: $display("B: %h", B);
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`ALU_REG_C: $display("C: %h", C);
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`ALU_REG_D: $display("D: %h", D);
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endcase
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$write("xxx");
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for (display_counter = 15; display_counter != 255; display_counter = display_counter - 1)
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case (display_counter[3:0])
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alu_last:
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if (alu_first == alu_last) $write("!");
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else $write("L");
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alu_first: $write("^");
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default: $write(".");
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endcase
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$display("");
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end
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`endif
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/*
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*
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* Setting up SRC1 register for operations
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*
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*/
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`ifdef SIM
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$display("setting up source 1 registers");
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`endif
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case (alu_op)
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`ALU_OP_2CMPL,
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`ALU_OP_1CMPL,
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`ALU_OP_INC,
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`ALU_OP_TEST_EQ,
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`ALU_OP_TEST_NEQ: begin
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case (alu_reg_src1)
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`ALU_REG_A: alu_src1 <= A[alu_first*4+:4];
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`ALU_REG_B: alu_src1 <= B[alu_first*4+:4];
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`ALU_REG_C: alu_src1 <= C[alu_first*4+:4];
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`ALU_REG_D: alu_src1 <= D[alu_first*4+:4];
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endcase
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end
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default: begin
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`ifdef SIM
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$display("no source 1 required");
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`endif
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end
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endcase
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/*
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*
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* Setting up SRC2 register for operations
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*
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*/
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case (alu_op)
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`ALU_OP_TEST_EQ,
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`ALU_OP_TEST_NEQ: begin
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case (alu_reg_src2)
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`ALU_REG_A: alu_src2 <= A[alu_first*4+:4];
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`ALU_REG_B: alu_src2 <= B[alu_first*4+:4];
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`ALU_REG_C: alu_src2 <= C[alu_first*4+:4];
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`ALU_REG_D: alu_src2 <= D[alu_first*4+:4];
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`ALU_REG_0: alu_src2 <= 0;
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endcase
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end
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default: begin
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`ifdef SIM
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$display("no source 2 required");
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`endif
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end
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endcase
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/*
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*
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* update internal carry
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*
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*/
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case (alu_op)
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/*
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* option 1: carry starts at 0 (not used yet)
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*/
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// alu_carry <= (decstate == `DEC_ALU_INIT)?0:Carry;
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/*
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* option 2: carry starts at 1
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*/
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`ALU_OP_2CMPL,
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`ALU_OP_1CMPL,
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`ALU_OP_INC,
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`ALU_OP_TEST_EQ,
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`ALU_OP_TEST_NEQ:
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alu_carry <= (decstate == `DEC_ALU_INIT)?1:Carry;
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/*
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* option 3: carry is always cleared
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*/
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`ALU_OP_1CMPL:
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Carry <= 0;
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endcase
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if (alu_last == alu_first) alu_next_cycle <= `BUSCMD_PC_READ;
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else alu_next_cycle <= `BUSCMD_NOP;
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end
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endcase
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