mirror of
https://github.com/sxpert/hp-saturn
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49 lines
No EOL
689 B
Verilog
49 lines
No EOL
689 B
Verilog
`ifndef _SATURN_ALU
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`define _SATURN_ALU
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/**************************************************************************************************
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*
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* Bus manager
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*
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*
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*
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*/
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module saturn_alu (
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// inputs
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input strobe,
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input reset,
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input [19:0] address,
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input [3:0] command,
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input [3:0] nibble_in,
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// outputs
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output [3:0] nibble_out,
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output bus_error
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);
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// processor registers
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reg [19:0] PC;
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reg [3:0] P;
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reg [15:0] ST;
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reg [3:0] HST;
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reg Carry;
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reg [19:0] RSTK[0:7];
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reg [19:0] D0;
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reg [19:0] D1;
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reg [63:0] A;
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reg [63:0] B;
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reg [63:0] C;
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reg [63:0] D;
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reg [63:0] R0;
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reg [63:0] R1;
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reg [63:0] R2;
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reg [63:0] R3;
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reg [63:0] R4;
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endmodule
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`endif |