mirror of
https://github.com/sxpert/hp-saturn
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26 lines
617 B
Verilog
26 lines
617 B
Verilog
/******************************************************************************
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* 03 RTNCC
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*
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*
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*/
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DECODE_RTNCC:
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if (runstate == `INSTR_READY)
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begin
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Carry <= 0;
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PC <= RSTK[rstk_ptr];
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RSTK[rstk_ptr] <= 0;
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rstk_ptr <= rstk_ptr - 1;
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bus_load_pc <= 1;
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runstate <= `NEXT_INSTR;
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`ifdef SIM
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$display("%05h RTNCC", saved_PC);
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`endif
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end
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// `ifdef SIM
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// else
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// begin
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// decode_error <= 1;
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// $display("RTNCC runstate %h", runstate);
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// end
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// `endif
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