mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-19 10:26:58 +01:00
cbfbe4eb3f
add add_cst and sub_cst alu opcodes port pointer math to use ALU make A[ab]x more readable
68 lines
No EOL
1.4 KiB
Verilog
68 lines
No EOL
1.4 KiB
Verilog
`ifndef _FIELDS
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`define _FIELDS
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`define T_SET 0
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`define T_TEST 1
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`define T_DIR_OUT 0
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`define T_DIR_IN 1
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`define T_PTR_0 0
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`define T_PTR_1 1
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`define T_REG_A 0
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`define T_REG_C 1
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`define T_FTYPE_FIELD 0
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`define T_TTYPE_LEN 1
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`define T_TABLE_A 0
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`define T_TABLE_B 1
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`define T_TABLE_F 2
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`define T_TABLE_Z 3 // unused
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`define T_FIELD_P 0
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`define T_FIELD_WP 1
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`define T_FIELD_XS 2
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`define T_FIELD_X 3
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`define T_FIELD_S 4
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`define T_FIELD_M 5
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`define T_FIELD_B 6
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`define T_FIELD_W 7
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`define T_FIELD_A 15
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`define ALU_OP_ZERO 0
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`define ALU_OP_COPY 1
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`define ALU_OP_EXCH 2
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`define ALU_OP_SHL 3
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`define ALU_OP_SHR 4
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`define ALU_OP_2CMPL 5
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`define ALU_OP_1CMPL 6
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`define ALU_OP_INC 8
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`define ALU_OP_DEC 9
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`define ALU_OP_ADD 10
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`define ALU_OP_SUB 11
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`define ALU_OP_ADD_CST 12
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`define ALU_OP_SUB_CST 13
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`define ALU_OP_TEST_EQ 14
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`define ALU_OP_TEST_NEQ 15
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`define ALU_REG_A 0
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`define ALU_REG_B 1
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`define ALU_REG_C 2
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`define ALU_REG_D 3
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`define ALU_REG_D0 4
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`define ALU_REG_D1 5
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// 6
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// 7
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`define ALU_REG_R0 8
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`define ALU_REG_R1 9
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`define ALU_REG_R2 10
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`define ALU_REG_R3 11
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`define ALU_REG_R4 12
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`define ALU_REG_CST 13
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`define ALU_REG_M 14
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`define ALU_REG_0 15
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`endif |