mirror of
https://github.com/sxpert/hp-saturn
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70 lines
No EOL
1.8 KiB
Verilog
70 lines
No EOL
1.8 KiB
Verilog
/*
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* Alu module
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* calculations are in here
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*/
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`include "fields.v"
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`DEC_ALU_INIT, `DEC_ALU_CONT: begin
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`ifdef SIM
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if (alu_debug) begin
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$display("------------------------ z_alu_phase_3 - Store results -------------------------");
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$display("SRC1 %h | SRC2 %h | RES1 %h | RES2 %h | RC %b | DEST %h | TMP %h | CARRY %b",
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alu_src1, alu_src2, alu_res1, alu_res2, alu_res_carry,
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alu_reg_dest, alu_tmp, alu_carry);
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end
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`endif
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/*
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* put the result in destination register
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*/
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case (alu_op)
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// cases where the result is useful
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`ALU_OP_ZERO,
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`ALU_OP_COPY,
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`ALU_OP_2CMPL,
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`ALU_OP_1CMPL,
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`ALU_OP_INC: begin
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case (alu_reg_dest)
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`ALU_REG_A: A[alu_first*4+:4] <= alu_res1;
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`ALU_REG_B: B[alu_first*4+:4] <= alu_res1;
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`ALU_REG_C: C[alu_first*4+:4] <= alu_res1;
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`ALU_REG_D: D[alu_first*4+:4] <= alu_res1;
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endcase
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alu_first <= (alu_first + 1) & 4'hF;
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end
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// cases where there's no result
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`ALU_OP_TEST_EQ,
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`ALU_OP_TEST_NEQ: begin
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alu_first <= (alu_first + 1) & 4'hF;
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end
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default: begin
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`ifdef SIM
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$display("ALU: operation not implemented");
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decode_error <= 1;
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`endif
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end
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endcase
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/*
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* handle carry TODO: check if there are operations that don't touch carry
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*/
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case (alu_op)
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// cases where carry is to be changed
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`ALU_OP_2CMPL,
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`ALU_OP_1CMPL,
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`ALU_OP_INC,
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`ALU_OP_TEST_EQ,
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`ALU_OP_TEST_NEQ: begin
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Carry <= alu_res_carry;
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end
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endcase
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if (alu_last == alu_first) begin
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// the alu is done
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next_cycle <= alu_next_cycle;
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decstate <= alu_return;
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alu_requested_halt <= alu_p1_halt | alu_p2_halt | alu_halt ;
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end else decstate <= `DEC_ALU_CONT;
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end |