mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-31 19:57:50 +01:00
72 lines
No EOL
1.5 KiB
Verilog
72 lines
No EOL
1.5 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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module saturn_bus_controller (
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i_clk,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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o_bus_clk_en,
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o_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in,
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o_debug_cycle,
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o_halt
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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output reg [0:0] o_bus_clk_en;
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output reg [0:0] o_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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output wire [0:0] o_debug_cycle;
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output wire [0:0] o_halt;
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reg [0:0] bus_error;
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initial bus_error = 0;
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// this should come from the debugger
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assign o_debug_cycle = 1'b0;
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assign o_halt = bus_error;
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always @(posedge i_clk) begin
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if (!o_debug_cycle) begin
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end
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if (i_reset) begin
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bus_error <= 1'b0;
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end
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end
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endmodule |