mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
161 lines
3 KiB
Verilog
161 lines
3 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`ifdef SIM
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module saturn_top;
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saturn_bus main_bus (
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.i_clk (clk),
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.i_clk_en (clk_en),
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.i_reset (reset),
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.o_halt (halt),
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.o_char_to_send (t_led)
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);
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wire [7:0] t_led;
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wire [7:0] led;
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reg [0:0] reset;
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wire [0:0] halt;
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reg [0:0] clk;
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initial begin
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$display("TOP : starting the simulation");
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clk = 0;
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reset = 1;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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reset = 0;
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$display("TOP : reset done, waiting for instructions");
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@(posedge halt);
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$display("TOP : instructed to stop, halt is %b", halt);
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$finish;
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end
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always
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#10 clk = (clk === 1'b0);
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reg [0:0] clk_en;
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reg [7:0] test;
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initial begin
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clk_en = 1'b1;
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test = 8'b1;
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end
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always @(posedge clk) begin
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test <= {test[6:0], test[7]};
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if (reset) begin
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clk_en <= 1'b1;
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test <= 8'b1;
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end
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end
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endmodule
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`else
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/*
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*
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*
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*
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*/
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module saturn_top (
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clk_25mhz,
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btn,
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led,
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wifi_gpio0
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);
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input wire [0:0] clk_25mhz;
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input wire [6:0] btn;
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output reg [7:0] led;
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output wire [0:0] wifi_gpio0;
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/* this is necessary, otherwise, the esp32 module reboots the fpga in passthrough */
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assign wifi_gpio0 = btn[0];
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saturn_bus main_bus (
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.i_clk (clk_25mhz),
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.i_clk_en (clk_en),
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.i_reset (reset),
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.o_halt (halt),
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.o_phase (phase),
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.o_cycle_ctr (cycle_ctr),
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.o_char_to_send (t_led)
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);
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reg [25:0] delay;
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reg [0:0] clk2;
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reg [0:0] clk_en;
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reg [0:0] reset;
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wire [0:0] halt;
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wire [1:0] phase;
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wire [31:0] cycle_ctr;
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wire [7:0] t_led;
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/* 1/4 s */
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`define DELAY_START 26'h20A1F0
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`define TEST_BIT 23
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/* 1/16 s */
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// `define DELAY_START 26'h08287C
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// `define TEST_BIT 21
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/* 1/32 s */
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// `define DELAY_START 26'h4143E
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// `define TEST_BIT 20
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initial begin
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led = 8'h01;
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delay = `DELAY_START;
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reset = 1'b1;
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clk2 = 1'b0;
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end
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always @(posedge clk_25mhz) begin
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delay <= delay + 26'b1;
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if (delay[`TEST_BIT]) begin
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delay <= `DELAY_START;
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reset <= btn[1];
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clk2 <= ~clk2;
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end
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if (!clk2) begin
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led <= { halt, cycle_ctr[4:0], phase};
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end
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if (clk2 && !halt) begin
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clk_en <= 1'b1;
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led <= t_led;
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end
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if (clk_en)
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clk_en <= 1'b0;
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end
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endmodule
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`endif
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