mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
67 lines
No EOL
2.2 KiB
Verilog
67 lines
No EOL
2.2 KiB
Verilog
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/******************************************************************************
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* A[ab]x
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*
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* lots of things there
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*
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*/
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DECODE_A, DECODE_A_FS:
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case (runstate)
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`RUN_DECODE: runstate <= `INSTR_START;
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`INSTR_START, `INSTR_STROBE: begin end
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`INSTR_READY:
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case (decstate)
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DECODE_A:
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begin
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t_field <= nibble;
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decstate <= DECODE_A_FS;
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runstate <= `INSTR_START;
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end
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DECODE_A_FS:
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begin
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case (nibble)
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4'h2:
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case (t_field)
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4'he:
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begin
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C[7:0] <= 0;
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`ifdef SIM
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$display("%5h C=0\tB", saved_PC);
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`endif
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end
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default:
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begin
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`ifdef SIM
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$display("A[ab]x.1 decstate %d %h %h", decstate, t_field, nibble);
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`endif
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decode_error <= 1;
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end
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endcase
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default:
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begin
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`ifdef SIM
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$display("A[ab]x.2 decstate %d %h %h", decstate, t_field, nibble);
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`endif
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decode_error <= 1;
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end
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endcase
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runstate <= `NEXT_INSTR;
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// decstate <= DECODE_START;
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end
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default:
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begin
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`ifdef SIM
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$display("A[ab]x.3 decstate %d %h", decstate, nibble);
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`endif
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decode_error <= 1;
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end
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endcase
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default:
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begin
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`ifdef SIM
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$display("A[ab]x.4 decstate %d runstate %d", decstate, runstate);
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`endif
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decode_error <= 1;
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end
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endcase |