mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-31 19:57:50 +01:00
aa95324ea9
(need to find a way to output the instruction representation)
26 lines
660 B
Verilog
26 lines
660 B
Verilog
/******************************************************************************
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* 3n[xxxxxx] LC (n) [xxxxxx]
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*
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*
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*/
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`include "decstates.v"
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`include "fields.v"
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`DEC_LC: begin
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alu_first <= P;
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alu_last <= (P + nb_in) & 4'hF;
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alu_reg_src1 <= `ALU_REG_MEM;
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alu_reg_dest <= `ALU_REG_C;
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alu_op <= `ALU_OP_COPY;
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// alu_debug <= 1;
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decstate <= `DEC_ALU_INIT;
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alu_return <= `DEC_START;
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// `ifdef SIM
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// $write("%5h LC (%h)\t%1h", inst_start_PC, t_cnt, nb_in);
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// for(t_ctr = 0; t_ctr != t_cnt; t_ctr ++)
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// $write("%1h", C[(((t_cnt - t_ctr - 4'h1)+P)%16)*4+:4]);
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// $write("\n");
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// `endif
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end
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